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stm32f429xx.h
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1 /**
2  ******************************************************************************
3  * @file stm32f429xx.h
4  * @author MCD Application Team
5  * @version V2.0.0
6  * @date 18-February-2014
7  * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
8  *
9  * This file contains:
10  * - Data structures and the address mapping for all peripherals
11  * - Peripheral's registers declarations and bits definition
12  * - Macros to access peripheral’s registers hardware
13  *
14  ******************************************************************************
15  * @attention
16  *
17  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
18  *
19  * Redistribution and use in source and binary forms, with or without modification,
20  * are permitted provided that the following conditions are met:
21  * 1. Redistributions of source code must retain the above copyright notice,
22  * this list of conditions and the following disclaimer.
23  * 2. Redistributions in binary form must reproduce the above copyright notice,
24  * this list of conditions and the following disclaimer in the documentation
25  * and/or other materials provided with the distribution.
26  * 3. Neither the name of STMicroelectronics nor the names of its contributors
27  * may be used to endorse or promote products derived from this software
28  * without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  *
41  ******************************************************************************
42  */
43 
44 /** @addtogroup CMSIS_Device
45  * @{
46  */
47 
48 /** @addtogroup stm32f429xx
49  * @{
50  */
51 
52 #ifndef __STM32F429xx_H
53 #define __STM32F429xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 /** @addtogroup Configuration_section_for_CMSIS
60  * @{
61  */
62 
63 /**
64  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65  */
66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< FPU present */
71 
72 /**
73  * @}
74  */
75 
76 /** @addtogroup Peripheral_interrupt_number_definition
77  * @{
78  */
79 
80 /**
81  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
82  * in @ref Library_configuration_section
83  */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89  BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90  UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91  SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92  DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93  PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94  SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97  PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98  TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
99  RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
100  FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101  RCC_IRQn = 5, /*!< RCC global Interrupt */
102  EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103  EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104  EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
105  EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106  EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107  DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
108  DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
109  DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
110  DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
111  DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
112  DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
113  DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
114  ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
115  CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
116  CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
117  CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
118  CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
119  EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120  TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
121  TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
122  TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
123  TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124  TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125  TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126  TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127  I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
128  I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129  I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
130  I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131  SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132  SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133  USART1_IRQn = 37, /*!< USART1 global Interrupt */
134  USART2_IRQn = 38, /*!< USART2 global Interrupt */
135  USART3_IRQn = 39, /*!< USART3 global Interrupt */
136  EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137  RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
138  OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
139  TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
140  TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
141  TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
142  TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
143  DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
144  FMC_IRQn = 48, /*!< FMC global Interrupt */
145  SDIO_IRQn = 49, /*!< SDIO global Interrupt */
146  TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
147  SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
148  UART4_IRQn = 52, /*!< UART4 global Interrupt */
149  UART5_IRQn = 53, /*!< UART5 global Interrupt */
150  TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
151  TIM7_IRQn = 55, /*!< TIM7 global interrupt */
152  DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
153  DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
154  DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
155  DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
156  DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
157  ETH_IRQn = 61, /*!< Ethernet global Interrupt */
158  ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
159  CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
160  CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
161  CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
162  CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
163  OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
164  DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
165  DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
166  DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
167  USART6_IRQn = 71, /*!< USART6 global interrupt */
168  I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
169  I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
170  OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
171  OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
172  OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
173  OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
174  DCMI_IRQn = 78, /*!< DCMI global interrupt */
175  HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
176  FPU_IRQn = 81, /*!< FPU global interrupt */
177  UART7_IRQn = 82, /*!< UART7 global interrupt */
178  UART8_IRQn = 83, /*!< UART8 global interrupt */
179  SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
180  SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
181  SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
182  SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
183  LTDC_IRQn = 88, /*!< LTDC global Interrupt */
184  LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
185  DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
186 } IRQn_Type;
187 
188 /**
189  * @}
190  */
191 
192 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
193 #include "system_stm32f4xx.h"
194 #include <stdint.h>
195 
196 /** @addtogroup Peripheral_registers_structures
197  * @{
198  */
199 
200 /**
201  * @brief Analog to Digital Converter
202  */
203 
204 typedef struct
205 {
206  __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
207  __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
208  __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
209  __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
210  __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
211  __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
212  __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
213  __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
214  __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
215  __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
216  __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
217  __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
218  __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
219  __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
220  __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
221  __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
222  __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
223  __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
224  __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
225  __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
226 } ADC_TypeDef;
227 
228 typedef struct
229 {
230  __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
231  __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
232  __IO uint32_t CDR; /*!< ADC common regular data register for dual
233  AND triple modes, Address offset: ADC1 base address + 0x308 */
234 } ADC_Common_TypeDef;
235 
236 
237 /**
238  * @brief Controller Area Network TxMailBox
239  */
240 
241 typedef struct
242 {
243  __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
244  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
245  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
246  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
247 } CAN_TxMailBox_TypeDef;
248 
249 /**
250  * @brief Controller Area Network FIFOMailBox
251  */
252 
253 typedef struct
254 {
255  __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259 } CAN_FIFOMailBox_TypeDef;
260 
261 /**
262  * @brief Controller Area Network FilterRegister
263  */
264 
265 typedef struct
266 {
267  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
268  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
269 } CAN_FilterRegister_TypeDef;
270 
271 /**
272  * @brief Controller Area Network
273  */
274 
275 typedef struct
276 {
277  __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
278  __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
279  __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
280  __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
281  __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
282  __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
283  __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
284  __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
285  uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
286  CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
287  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
288  uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
289  __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
290  __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
291  uint32_t RESERVED2; /*!< Reserved, 0x208 */
292  __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
293  uint32_t RESERVED3; /*!< Reserved, 0x210 */
294  __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
295  uint32_t RESERVED4; /*!< Reserved, 0x218 */
296  __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
297  uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
298  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
299 } CAN_TypeDef;
300 
301 /**
302  * @brief CRC calculation unit
303  */
304 
305 typedef struct
306 {
307  __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
308  __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
309  uint8_t RESERVED0; /*!< Reserved, 0x05 */
310  uint16_t RESERVED1; /*!< Reserved, 0x06 */
311  __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
312 } CRC_TypeDef;
313 
314 /**
315  * @brief Digital to Analog Converter
316  */
317 
318 typedef struct
319 {
320  __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
321  __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
322  __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
323  __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
324  __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
325  __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
326  __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
327  __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
328  __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
329  __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
330  __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
331  __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
332  __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
333  __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
334 } DAC_TypeDef;
335 
336 /**
337  * @brief Debug MCU
338  */
339 
340 typedef struct
341 {
342  __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
343  __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
344  __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
345  __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
346 }DBGMCU_TypeDef;
347 
348 /**
349  * @brief DCMI
350  */
351 
352 typedef struct
353 {
354  __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
355  __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
356  __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
357  __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
358  __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
359  __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
360  __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
361  __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
362  __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
363  __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
364  __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
365 } DCMI_TypeDef;
366 
367 /**
368  * @brief DMA Controller
369  */
370 
371 typedef struct
372 {
373  __IO uint32_t CR; /*!< DMA stream x configuration register */
374  __IO uint32_t NDTR; /*!< DMA stream x number of data register */
375  __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
376  __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
377  __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
378  __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
379 } DMA_Stream_TypeDef;
380 
381 typedef struct
382 {
383  __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
384  __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
385  __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
386  __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
387 } DMA_TypeDef;
388 
389 /**
390  * @brief DMA2D Controller
391  */
392 
393 typedef struct
394 {
395  __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
396  __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
397  __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
398  __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
399  __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
400  __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
401  __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
402  __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
403  __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
404  __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
405  __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
406  __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
407  __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
408  __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
409  __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
410  __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
411  __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
412  __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
413  __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
414  __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
415  uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
416  __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
417  __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
418 } DMA2D_TypeDef;
419 
420 /**
421  * @brief Ethernet MAC
422  */
423 
424 typedef struct
425 {
426  __IO uint32_t MACCR;
427  __IO uint32_t MACFFR;
428  __IO uint32_t MACHTHR;
429  __IO uint32_t MACHTLR;
430  __IO uint32_t MACMIIAR;
431  __IO uint32_t MACMIIDR;
432  __IO uint32_t MACFCR;
433  __IO uint32_t MACVLANTR; /* 8 */
434  uint32_t RESERVED0[2];
435  __IO uint32_t MACRWUFFR; /* 11 */
436  __IO uint32_t MACPMTCSR;
437  uint32_t RESERVED1[2];
438  __IO uint32_t MACSR; /* 15 */
439  __IO uint32_t MACIMR;
440  __IO uint32_t MACA0HR;
441  __IO uint32_t MACA0LR;
442  __IO uint32_t MACA1HR;
443  __IO uint32_t MACA1LR;
444  __IO uint32_t MACA2HR;
445  __IO uint32_t MACA2LR;
446  __IO uint32_t MACA3HR;
447  __IO uint32_t MACA3LR; /* 24 */
448  uint32_t RESERVED2[40];
449  __IO uint32_t MMCCR; /* 65 */
450  __IO uint32_t MMCRIR;
451  __IO uint32_t MMCTIR;
452  __IO uint32_t MMCRIMR;
453  __IO uint32_t MMCTIMR; /* 69 */
454  uint32_t RESERVED3[14];
455  __IO uint32_t MMCTGFSCCR; /* 84 */
456  __IO uint32_t MMCTGFMSCCR;
457  uint32_t RESERVED4[5];
458  __IO uint32_t MMCTGFCR;
459  uint32_t RESERVED5[10];
460  __IO uint32_t MMCRFCECR;
461  __IO uint32_t MMCRFAECR;
462  uint32_t RESERVED6[10];
463  __IO uint32_t MMCRGUFCR;
464  uint32_t RESERVED7[334];
465  __IO uint32_t PTPTSCR;
466  __IO uint32_t PTPSSIR;
467  __IO uint32_t PTPTSHR;
468  __IO uint32_t PTPTSLR;
469  __IO uint32_t PTPTSHUR;
470  __IO uint32_t PTPTSLUR;
471  __IO uint32_t PTPTSAR;
472  __IO uint32_t PTPTTHR;
473  __IO uint32_t PTPTTLR;
474  __IO uint32_t RESERVED8;
475  __IO uint32_t PTPTSSR;
476  uint32_t RESERVED9[565];
477  __IO uint32_t DMABMR;
478  __IO uint32_t DMATPDR;
479  __IO uint32_t DMARPDR;
480  __IO uint32_t DMARDLAR;
481  __IO uint32_t DMATDLAR;
482  __IO uint32_t DMASR;
483  __IO uint32_t DMAOMR;
484  __IO uint32_t DMAIER;
485  __IO uint32_t DMAMFBOCR;
486  __IO uint32_t DMARSWTR;
487  uint32_t RESERVED10[8];
488  __IO uint32_t DMACHTDR;
489  __IO uint32_t DMACHRDR;
490  __IO uint32_t DMACHTBAR;
491  __IO uint32_t DMACHRBAR;
492 } ETH_TypeDef;
493 
494 /**
495  * @brief External Interrupt/Event Controller
496  */
497 
498 typedef struct
499 {
500  __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
501  __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
502  __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
503  __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
504  __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
505  __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
506 } EXTI_TypeDef;
507 
508 /**
509  * @brief FLASH Registers
510  */
511 
512 typedef struct
513 {
514  __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
515  __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
516  __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
517  __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
518  __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
519  __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
520  __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
521 } FLASH_TypeDef;
522 
523 /**
524  * @brief Flexible Memory Controller
525  */
526 
527 typedef struct
528 {
529  __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
530 } FMC_Bank1_TypeDef;
531 
532 /**
533  * @brief Flexible Memory Controller Bank1E
534  */
535 
536 typedef struct
537 {
538  __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
539 } FMC_Bank1E_TypeDef;
540 
541 /**
542  * @brief Flexible Memory Controller Bank2
543  */
544 
545 typedef struct
546 {
547  __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
548  __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
549  __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
550  __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
551  uint32_t RESERVED0; /*!< Reserved, 0x70 */
552  __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
553  uint32_t RESERVED1; /*!< Reserved, 0x78 */
554  uint32_t RESERVED2; /*!< Reserved, 0x7C */
555  __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
556  __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
557  __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
558  __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
559  uint32_t RESERVED3; /*!< Reserved, 0x90 */
560  __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
561 } FMC_Bank2_3_TypeDef;
562 
563 /**
564  * @brief Flexible Memory Controller Bank4
565  */
566 
567 typedef struct
568 {
569  __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
570  __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
571  __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
572  __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
573  __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
574 } FMC_Bank4_TypeDef;
575 
576 /**
577  * @brief Flexible Memory Controller Bank5_6
578  */
579 
580 typedef struct
581 {
582  __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
583  __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
584  __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
585  __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
586  __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
587 } FMC_Bank5_6_TypeDef;
588 
589 /**
590  * @brief General Purpose I/O
591  */
592 
593 typedef struct
594 {
595  __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
596  __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
597  __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
598  __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
599  __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
600  __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
601  __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
602  __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
603  __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
604  __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
605 } GPIO_TypeDef;
606 
607 /**
608  * @brief System configuration controller
609  */
610 
611 typedef struct
612 {
613  __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
614  __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
615  __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
616  uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
617  __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
618 } SYSCFG_TypeDef;
619 
620 /**
621  * @brief Inter-integrated Circuit Interface
622  */
623 
624 typedef struct
625 {
626  __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
627  __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
628  __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
629  __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
630  __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
631  __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
632  __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
633  __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
634  __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
635  __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
636 } I2C_TypeDef;
637 
638 /**
639  * @brief Independent WATCHDOG
640  */
641 
642 typedef struct
643 {
644  __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
645  __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
646  __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
647  __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
648 } IWDG_TypeDef;
649 
650 /**
651  * @brief LCD-TFT Display Controller
652  */
653 
654 typedef struct
655 {
656  uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
657  __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
658  __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
659  __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
660  __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
661  __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
662  uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
663  __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
664  uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
665  __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
666  uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
667  __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
668  __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
669  __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
670  __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
671  __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
672  __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
673 } LTDC_TypeDef;
674 
675 /**
676  * @brief LCD-TFT Display layer x Controller
677  */
678 
679 typedef struct
680 {
681  __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
682  __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
683  __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
684  __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
685  __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
686  __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
687  __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
688  __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
689  uint32_t RESERVED0[2]; /*!< Reserved */
690  __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
691  __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
692  __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
693  uint32_t RESERVED1[3]; /*!< Reserved */
694  __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
695 
696 } LTDC_Layer_TypeDef;
697 
698 /**
699  * @brief Power Control
700  */
701 
702 typedef struct
703 {
704  __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
705  __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
706 } PWR_TypeDef;
707 
708 /**
709  * @brief Reset and Clock Control
710  */
711 
712 typedef struct
713 {
714  __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
715  __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
716  __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
717  __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
718  __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
719  __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
720  __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
721  uint32_t RESERVED0; /*!< Reserved, 0x1C */
722  __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
723  __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
724  uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
725  __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
726  __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
727  __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
728  uint32_t RESERVED2; /*!< Reserved, 0x3C */
729  __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
730  __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
731  uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
732  __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
733  __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
734  __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
735  uint32_t RESERVED4; /*!< Reserved, 0x5C */
736  __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
737  __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
738  uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
739  __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
740  __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
741  uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
742  __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
743  __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
744  __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
745  __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
746 
747 } RCC_TypeDef;
748 
749 /**
750  * @brief Real-Time Clock
751  */
752 
753 typedef struct
754 {
755  __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
756  __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
757  __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
758  __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
759  __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
760  __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
761  __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
762  __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
763  __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
764  __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
765  __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
766  __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
767  __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
768  __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
769  __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
770  __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
771  __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
772  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
773  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
774  uint32_t RESERVED7; /*!< Reserved, 0x4C */
775  __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
776  __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
777  __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
778  __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
779  __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
780  __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
781  __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
782  __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
783  __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
784  __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
785  __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
786  __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
787  __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
788  __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
789  __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
790  __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
791  __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
792  __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
793  __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
794  __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
795 } RTC_TypeDef;
796 
797 /**
798  * @brief Serial Audio Interface
799  */
800 
801 typedef struct
802 {
803  __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
804 } SAI_TypeDef;
805 
806 typedef struct
807 {
808  __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
809  __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
810  __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
811  __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
812  __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
813  __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
814  __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
815  __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
816 } SAI_Block_TypeDef;
817 
818 /**
819  * @brief SD host Interface
820  */
821 
822 typedef struct
823 {
824  __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
825  __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
826  __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
827  __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
828  __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
829  __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
830  __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
831  __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
832  __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
833  __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
834  __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
835  __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
836  __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
837  __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
838  __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
839  __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
840  uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
841  __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
842  uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
843  __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
844 } SDIO_TypeDef;
845 
846 /**
847  * @brief Serial Peripheral Interface
848  */
849 
850 typedef struct
851 {
852  __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
853  __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
854  __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
855  __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
856  __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
857  __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
858  __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
859  __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
860  __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
861 } SPI_TypeDef;
862 
863 /**
864  * @brief TIM
865  */
866 
867 typedef struct
868 {
869  __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
870  __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
871  __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
872  __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
873  __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
874  __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
875  __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
876  __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
877  __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
878  __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
879  __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
880  __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
881  __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
882  __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
883  __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
884  __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
885  __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
886  __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
887  __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
888  __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
889  __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
890 } TIM_TypeDef;
891 
892 /**
893  * @brief Universal Synchronous Asynchronous Receiver Transmitter
894  */
895 
896 typedef struct
897 {
898  __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
899  __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
900  __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
901  __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
902  __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
903  __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
904  __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
905 } USART_TypeDef;
906 
907 /**
908  * @brief Window WATCHDOG
909  */
910 
911 typedef struct
912 {
913  __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
914  __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
915  __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
916 } WWDG_TypeDef;
917 
918 
919 /**
920  * @brief RNG
921  */
922 
923 typedef struct
924 {
925  __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
926  __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
927  __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
928 } RNG_TypeDef;
929 
930 
931 /**
932  * @brief __USB_OTG_Core_register
933  */
934 typedef struct
935 {
936  __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
937  __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
938  __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
939  __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
940  __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
941  __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
942  __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
943  __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
944  __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
945  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
946  __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
947  __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
948  uint32_t Reserved30[2]; /* Reserved 030h*/
949  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
950  __IO uint32_t CID; /* User ID Register 03Ch*/
951  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
952  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
953  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
954 }
955 USB_OTG_GlobalTypeDef;
956 
957 
958 /**
959  * @brief __device_Registers
960  */
961 typedef struct
962 {
963  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
964  __IO uint32_t DCTL; /* dev Control Register 804h*/
965  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
966  uint32_t Reserved0C; /* Reserved 80Ch*/
967  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
968  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
969  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
970  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
971  uint32_t Reserved20; /* Reserved 820h*/
972  uint32_t Reserved9; /* Reserved 824h*/
973  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
974  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
975  __IO uint32_t DTHRCTL; /* dev thr 830h*/
976  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
977  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
978  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
979  uint32_t Reserved40; /* dedicated EP mask 840h*/
980  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
981  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
982  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
983 }
984 USB_OTG_DeviceTypeDef;
985 
986 
987 /**
988  * @brief __IN_Endpoint-Specific_Register
989  */
990 typedef struct
991 {
992  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
993  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
994  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
995  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
996  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
997  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
998  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
999  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1000 }
1001 USB_OTG_INEndpointTypeDef;
1002 
1003 
1004 /**
1005  * @brief __OUT_Endpoint-Specific_Registers
1006  */
1007 typedef struct
1008 {
1009  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1010  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1011  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1012  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1013  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1014  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1015  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1016 }
1017 USB_OTG_OUTEndpointTypeDef;
1018 
1019 
1020 /**
1021  * @brief __Host_Mode_Register_Structures
1022  */
1023 typedef struct
1024 {
1025  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1026  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1027  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1028  uint32_t Reserved40C; /* Reserved 40Ch*/
1029  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1030  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1031  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1032 }
1033 USB_OTG_HostTypeDef;
1034 
1035 /**
1036  * @brief __Host_Channel_Specific_Registers
1037  */
1038 typedef struct
1039 {
1040  __IO uint32_t HCCHAR;
1041  __IO uint32_t HCSPLT;
1042  __IO uint32_t HCINT;
1043  __IO uint32_t HCINTMSK;
1044  __IO uint32_t HCTSIZ;
1045  __IO uint32_t HCDMA;
1046  uint32_t Reserved[2];
1047 }
1048 USB_OTG_HostChannelTypeDef;
1049 /**
1050  * @}
1051  */
1052 
1053 /** @addtogroup Peripheral_memory_map
1054  * @{
1055  */
1056 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
1057 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1058 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
1059 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
1060 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
1061 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
1062 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
1063 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
1064 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
1065 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
1066 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
1067 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
1068 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1069 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
1070 
1071 /* Legacy defines */
1072 #define SRAM_BASE SRAM1_BASE
1073 #define SRAM_BB_BASE SRAM1_BB_BASE
1074 
1075 
1076 /*!< Peripheral memory map */
1077 #define APB1PERIPH_BASE PERIPH_BASE
1078 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1079 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1080 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1081 
1082 /*!< APB1 peripherals */
1083 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1084 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1085 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1086 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1087 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1088 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1089 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1090 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1091 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1092 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1093 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1094 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1095 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
1096 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1097 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1098 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
1099 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1100 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1101 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1102 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1103 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1104 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1105 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1106 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1107 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1108 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1109 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1110 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
1111 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
1112 
1113 /*!< APB2 peripherals */
1114 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1115 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1116 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1117 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1118 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1119 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1120 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1121 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1122 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1123 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1124 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
1125 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1126 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1127 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1128 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1129 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1130 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
1131 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
1132 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
1133 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1134 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1135 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
1136 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
1137 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
1138 
1139 /*!< AHB1 peripherals */
1140 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1141 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1142 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1143 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1144 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1145 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1146 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1147 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1148 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1149 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
1150 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
1151 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1152 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1153 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1154 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1155 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1156 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1157 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1158 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1159 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1160 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1161 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1162 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1163 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1164 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1165 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1166 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1167 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1168 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1169 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1170 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1171 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1172 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1173 #define ETH_MAC_BASE (ETH_BASE)
1174 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1175 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1176 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1177 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
1178 
1179 /*!< AHB2 peripherals */
1180 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1181 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1182 
1183 /*!< FMC Bankx registers base address */
1184 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
1185 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
1186 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
1187 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
1188 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
1189 
1190 /* Debug MCU registers base address */
1191 #define DBGMCU_BASE ((uint32_t )0xE0042000)
1192 
1193 /*!< USB registers base address */
1194 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
1195 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
1196 
1197 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
1198 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
1199 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
1200 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
1201 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
1202 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
1203 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
1204 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
1205 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
1206 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
1207 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
1208 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
1209 
1210 /**
1211  * @}
1212  */
1213 
1214 /** @addtogroup Peripheral_declaration
1215  * @{
1216  */
1217 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1218 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1219 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1220 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1221 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1222 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1223 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1224 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1225 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1226 #define RTC ((RTC_TypeDef *) RTC_BASE)
1227 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1228 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1229 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1230 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1231 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1232 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1233 #define USART2 ((USART_TypeDef *) USART2_BASE)
1234 #define USART3 ((USART_TypeDef *) USART3_BASE)
1235 #define UART4 ((USART_TypeDef *) UART4_BASE)
1236 #define UART5 ((USART_TypeDef *) UART5_BASE)
1237 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1238 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1239 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1240 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1241 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1242 #define PWR ((PWR_TypeDef *) PWR_BASE)
1243 #define DAC ((DAC_TypeDef *) DAC_BASE)
1244 #define UART7 ((USART_TypeDef *) UART7_BASE)
1245 #define UART8 ((USART_TypeDef *) UART8_BASE)
1246 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1247 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1248 #define USART1 ((USART_TypeDef *) USART1_BASE)
1249 #define USART6 ((USART_TypeDef *) USART6_BASE)
1250 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1251 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1252 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1253 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1254 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1255 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1256 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1257 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1258 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1259 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1260 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1261 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1262 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1263 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1264 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1265 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1266 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1267 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1268 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1269 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1270 
1271 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1272 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1273 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1274 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1275 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1276 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1277 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1278 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1279 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1280 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1281 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1282 #define CRC ((CRC_TypeDef *) CRC_BASE)
1283 #define RCC ((RCC_TypeDef *) RCC_BASE)
1284 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1285 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1286 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1287 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1288 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1289 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1290 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1291 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1292 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1293 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1294 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1295 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1296 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1297 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1298 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1299 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1300 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1301 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1302 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1303 #define ETH ((ETH_TypeDef *) ETH_BASE)
1304 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1305 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1306 #define RNG ((RNG_TypeDef *) RNG_BASE)
1307 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1308 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1309 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1310 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1311 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1312 
1313 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1314 
1315 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1316 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1317 
1318 /**
1319  * @}
1320  */
1321 
1322 /** @addtogroup Exported_constants
1323  * @{
1324  */
1325 
1326  /** @addtogroup Peripheral_Registers_Bits_Definition
1327  * @{
1328  */
1329 
1330 /******************************************************************************/
1331 /* Peripheral Registers_Bits_Definition */
1332 /******************************************************************************/
1333 
1334 /******************************************************************************/
1335 /* */
1336 /* Analog to Digital Converter */
1337 /* */
1338 /******************************************************************************/
1339 /******************** Bit definition for ADC_SR register ********************/
1340 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
1341 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
1342 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
1343 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
1344 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
1345 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
1346 
1347 /******************* Bit definition for ADC_CR1 register ********************/
1348 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1349 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1350 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1351 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1352 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1353 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1354 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1355 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1356 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1357 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1358 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1359 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1360 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1361 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1362 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1363 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1364 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1365 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1366 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1367 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1368 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1369 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1370 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1371 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1372 
1373 /******************* Bit definition for ADC_CR2 register ********************/
1374 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1375 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1376 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1377 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1378 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1379 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1380 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1381 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1382 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1383 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1384 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1385 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1386 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1387 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1388 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1389 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1390 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1391 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1392 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1393 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1394 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1395 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1396 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1397 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1398 
1399 /****************** Bit definition for ADC_SMPR1 register *******************/
1400 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1401 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1402 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1403 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1404 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1405 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1406 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1407 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1408 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1409 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1410 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1411 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1412 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1413 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1414 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1415 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1416 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1417 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1418 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1419 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1420 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1421 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1422 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1423 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1424 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1425 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1426 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1427 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1428 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1429 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1430 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1431 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1432 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1433 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1434 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1435 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1436 
1437 /****************** Bit definition for ADC_SMPR2 register *******************/
1438 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1439 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1440 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1441 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1442 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1443 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1444 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1445 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1446 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1447 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1448 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1449 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1450 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1451 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1452 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1453 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1454 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1455 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1456 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1457 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1458 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1459 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1460 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1461 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1462 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1463 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1464 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1465 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1466 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1467 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1468 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1469 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1470 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1471 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1472 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1473 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1474 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1475 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1476 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1477 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1478 
1479 /****************** Bit definition for ADC_JOFR1 register *******************/
1480 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
1481 
1482 /****************** Bit definition for ADC_JOFR2 register *******************/
1483 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
1484 
1485 /****************** Bit definition for ADC_JOFR3 register *******************/
1486 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
1487 
1488 /****************** Bit definition for ADC_JOFR4 register *******************/
1489 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
1490 
1491 /******************* Bit definition for ADC_HTR register ********************/
1492 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
1493 
1494 /******************* Bit definition for ADC_LTR register ********************/
1495 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
1496 
1497 /******************* Bit definition for ADC_SQR1 register *******************/
1498 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1499 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1500 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1501 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1502 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1503 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1504 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1505 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1506 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1507 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1508 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1509 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1510 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1511 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1512 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1513 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1514 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1515 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1516 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1517 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1518 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1519 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1520 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1521 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1522 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1523 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1524 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1525 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1526 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1527 
1528 /******************* Bit definition for ADC_SQR2 register *******************/
1529 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1530 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1531 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1532 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1533 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1534 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1535 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1536 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1537 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1538 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1539 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1540 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1541 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1542 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1543 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1544 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1545 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1546 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1547 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1548 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1549 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1550 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1551 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1552 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1553 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1554 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1555 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1556 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1557 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1558 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1559 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1560 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1561 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1562 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1563 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1564 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1565 
1566 /******************* Bit definition for ADC_SQR3 register *******************/
1567 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1568 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1569 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1570 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1571 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1572 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1573 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1574 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1575 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1576 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1577 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1578 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1579 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1580 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1581 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1582 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1583 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1584 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1585 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1586 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1587 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1588 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1589 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1590 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1591 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1592 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1593 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1594 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1595 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1596 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1597 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1598 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1599 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1600 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1601 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1602 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1603 
1604 /******************* Bit definition for ADC_JSQR register *******************/
1605 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1606 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1607 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1608 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1609 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1610 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1611 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1612 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1613 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1614 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1615 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1616 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1617 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1618 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1619 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1620 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1621 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1622 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1623 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1624 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1625 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1626 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1627 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1628 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1629 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1630 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1631 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1632 
1633 /******************* Bit definition for ADC_JDR1 register *******************/
1634 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1635 
1636 /******************* Bit definition for ADC_JDR2 register *******************/
1637 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1638 
1639 /******************* Bit definition for ADC_JDR3 register *******************/
1640 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1641 
1642 /******************* Bit definition for ADC_JDR4 register *******************/
1643 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
1644 
1645 /******************** Bit definition for ADC_DR register ********************/
1646 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1647 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1648 
1649 /******************* Bit definition for ADC_CSR register ********************/
1650 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1651 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1652 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1653 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1654 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1655 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1656 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1657 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1658 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1659 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1660 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1661 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1662 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1663 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1664 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1665 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1666 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1667 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1668 
1669 /******************* Bit definition for ADC_CCR register ********************/
1670 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1671 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1672 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1673 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1674 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1675 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1676 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1677 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1678 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1679 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1680 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1681 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1682 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1683 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1684 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1685 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1686 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1687 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1688 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1689 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1690 
1691 /******************* Bit definition for ADC_CDR register ********************/
1692 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1693 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1694 
1695 /******************************************************************************/
1696 /* */
1697 /* Controller Area Network */
1698 /* */
1699 /******************************************************************************/
1700 /*!<CAN control and status registers */
1701 /******************* Bit definition for CAN_MCR register ********************/
1702 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
1703 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
1704 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
1705 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
1706 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
1707 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
1708 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
1709 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
1710 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
1711 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
1712 /******************* Bit definition for CAN_MSR register ********************/
1713 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
1714 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
1715 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
1716 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
1717 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
1718 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
1719 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
1720 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
1721 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
1722 
1723 /******************* Bit definition for CAN_TSR register ********************/
1724 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1725 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1726 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1727 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1728 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1729 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1730 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1731 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1732 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1733 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1734 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1735 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1736 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1737 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1738 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1739 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1740 
1741 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1742 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1743 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1744 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1745 
1746 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1747 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1748 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1749 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1750 
1751 /******************* Bit definition for CAN_RF0R register *******************/
1752 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
1753 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
1754 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
1755 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
1756 
1757 /******************* Bit definition for CAN_RF1R register *******************/
1758 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
1759 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
1760 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
1761 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
1762 
1763 /******************** Bit definition for CAN_IER register *******************/
1764 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1765 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1766 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1767 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1768 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1769 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1770 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1771 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1772 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1773 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1774 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1775 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1776 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1777 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1778 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
1779 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
1780 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
1781 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
1782 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
1783 
1784 
1785 /******************** Bit definition for CAN_ESR register *******************/
1786 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1787 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1788 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1789 
1790 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1791 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1792 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1793 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1794 
1795 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1796 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1797 
1798 /******************* Bit definition for CAN_BTR register ********************/
1799 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1800 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1801 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1802 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1803 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1804 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1805 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1806 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1807 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1808 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1809 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1810 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1811 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1812 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1813 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1814 
1815 
1816 /*!<Mailbox registers */
1817 /****************** Bit definition for CAN_TI0R register ********************/
1818 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1819 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1820 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1821 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1822 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1823 
1824 /****************** Bit definition for CAN_TDT0R register *******************/
1825 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1826 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1827 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1828 
1829 /****************** Bit definition for CAN_TDL0R register *******************/
1830 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1831 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1832 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1833 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1834 
1835 /****************** Bit definition for CAN_TDH0R register *******************/
1836 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1837 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1838 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1839 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1840 
1841 /******************* Bit definition for CAN_TI1R register *******************/
1842 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1843 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1844 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1845 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1846 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1847 
1848 /******************* Bit definition for CAN_TDT1R register ******************/
1849 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1850 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1851 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1852 
1853 /******************* Bit definition for CAN_TDL1R register ******************/
1854 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1855 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1856 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1857 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1858 
1859 /******************* Bit definition for CAN_TDH1R register ******************/
1860 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1861 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1862 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1863 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1864 
1865 /******************* Bit definition for CAN_TI2R register *******************/
1866 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1867 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1868 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1869 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1870 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1871 
1872 /******************* Bit definition for CAN_TDT2R register ******************/
1873 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1874 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1875 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1876 
1877 /******************* Bit definition for CAN_TDL2R register ******************/
1878 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1879 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1880 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1881 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1882 
1883 /******************* Bit definition for CAN_TDH2R register ******************/
1884 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1885 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1886 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1887 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1888 
1889 /******************* Bit definition for CAN_RI0R register *******************/
1890 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1891 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1892 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1893 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1894 
1895 /******************* Bit definition for CAN_RDT0R register ******************/
1896 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1897 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1898 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1899 
1900 /******************* Bit definition for CAN_RDL0R register ******************/
1901 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1902 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1903 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1904 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1905 
1906 /******************* Bit definition for CAN_RDH0R register ******************/
1907 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1908 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1909 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1910 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1911 
1912 /******************* Bit definition for CAN_RI1R register *******************/
1913 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1914 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1915 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1916 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1917 
1918 /******************* Bit definition for CAN_RDT1R register ******************/
1919 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1920 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1921 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1922 
1923 /******************* Bit definition for CAN_RDL1R register ******************/
1924 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1925 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1926 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1927 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1928 
1929 /******************* Bit definition for CAN_RDH1R register ******************/
1930 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1931 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1932 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1933 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1934 
1935 /*!<CAN filter registers */
1936 /******************* Bit definition for CAN_FMR register ********************/
1937 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
1938 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
1939 
1940 /******************* Bit definition for CAN_FM1R register *******************/
1941 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
1942 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
1943 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
1944 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
1945 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
1946 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
1947 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
1948 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
1949 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
1950 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
1951 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
1952 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
1953 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
1954 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
1955 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
1956 
1957 /******************* Bit definition for CAN_FS1R register *******************/
1958 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
1959 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
1960 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
1961 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
1962 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
1963 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
1964 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
1965 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
1966 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
1967 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
1968 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
1969 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
1970 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
1971 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
1972 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
1973 
1974 /****************** Bit definition for CAN_FFA1R register *******************/
1975 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
1976 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
1977 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
1978 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
1979 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
1980 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
1981 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
1982 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
1983 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
1984 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
1985 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
1986 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
1987 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
1988 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
1989 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
1990 
1991 /******************* Bit definition for CAN_FA1R register *******************/
1992 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
1993 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
1994 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
1995 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
1996 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
1997 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
1998 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
1999 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
2000 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
2001 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
2002 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
2003 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
2004 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
2005 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
2006 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
2007 
2008 /******************* Bit definition for CAN_F0R1 register *******************/
2009 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2010 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2011 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2012 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2013 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2014 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2015 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2016 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2017 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2018 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2019 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2020 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2021 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2022 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2023 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2024 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2025 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2026 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2027 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2028 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2029 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2030 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2031 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2032 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2033 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2034 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2035 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2036 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2037 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2038 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2039 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2040 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2041 
2042 /******************* Bit definition for CAN_F1R1 register *******************/
2043 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2044 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2045 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2046 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2047 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2048 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2049 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2050 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2051 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2052 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2053 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2054 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2055 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2056 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2057 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2058 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2059 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2060 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2061 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2062 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2063 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2064 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2065 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2066 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2067 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2068 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2069 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2070 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2071 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2072 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2073 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2074 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2075 
2076 /******************* Bit definition for CAN_F2R1 register *******************/
2077 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2078 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2079 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2080 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2081 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2082 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2083 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2084 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2085 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2086 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2087 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2088 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2089 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2090 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2091 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2092 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2093 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2094 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2095 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2096 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2097 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2098 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2099 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2100 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2101 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2102 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2103 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2104 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2105 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2106 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2107 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2108 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2109 
2110 /******************* Bit definition for CAN_F3R1 register *******************/
2111 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2112 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2113 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2114 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2115 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2116 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2117 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2118 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2119 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2120 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2121 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2122 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2123 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2124 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2125 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2126 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2127 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2128 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2129 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2130 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2131 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2132 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2133 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2134 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2135 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2136 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2137 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2138 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2139 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2140 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2141 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2142 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2143 
2144 /******************* Bit definition for CAN_F4R1 register *******************/
2145 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2146 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2147 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2148 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2149 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2150 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2151 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2152 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2153 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2154 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2155 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2156 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2157 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2158 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2159 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2160 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2161 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2162 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2163 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2164 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2165 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2166 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2167 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2168 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2169 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2170 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2171 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2172 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2173 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2174 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2175 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2176 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2177 
2178 /******************* Bit definition for CAN_F5R1 register *******************/
2179 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2180 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2181 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2182 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2183 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2184 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2185 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2186 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2187 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2188 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2189 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2190 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2191 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2192 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2193 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2194 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2195 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2196 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2197 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2198 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2199 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2200 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2201 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2202 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2203 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2204 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2205 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2206 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2207 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2208 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2209 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2210 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2211 
2212 /******************* Bit definition for CAN_F6R1 register *******************/
2213 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2214 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2215 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2216 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2217 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2218 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2219 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2220 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2221 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2222 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2223 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2224 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2225 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2226 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2227 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2228 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2229 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2230 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2231 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2232 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2233 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2234 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2235 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2236 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2237 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2238 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2239 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2240 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2241 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2242 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2243 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2244 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2245 
2246 /******************* Bit definition for CAN_F7R1 register *******************/
2247 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2248 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2249 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2250 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2251 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2252 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2253 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2254 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2255 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2256 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2257 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2258 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2259 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2260 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2261 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2262 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2263 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2264 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2265 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2266 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2267 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2268 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2269 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2270 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2271 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2272 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2273 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2274 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2275 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2276 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2277 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2278 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2279 
2280 /******************* Bit definition for CAN_F8R1 register *******************/
2281 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2282 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2283 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2284 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2285 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2286 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2287 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2288 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2289 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2290 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2291 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2292 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2293 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2294 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2295 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2296 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2297 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2298 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2299 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2300 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2301 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2302 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2303 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2304 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2305 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2306 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2307 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2308 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2309 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2310 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2311 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2312 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2313 
2314 /******************* Bit definition for CAN_F9R1 register *******************/
2315 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2316 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2317 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2318 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2319 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2320 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2321 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2322 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2323 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2324 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2325 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2326 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2327 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2328 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2329 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2330 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2331 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2332 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2333 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2334 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2335 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2336 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2337 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2338 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2339 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2340 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2341 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2342 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2343 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2344 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2345 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2346 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2347 
2348 /******************* Bit definition for CAN_F10R1 register ******************/
2349 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2350 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2351 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2352 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2353 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2354 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2355 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2356 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2357 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2358 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2359 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2360 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2361 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2362 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2363 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2364 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2365 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2366 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2367 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2368 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2369 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2370 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2371 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2372 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2373 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2374 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2375 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2376 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2377 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2378 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2379 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2380 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2381 
2382 /******************* Bit definition for CAN_F11R1 register ******************/
2383 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2384 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2385 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2386 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2387 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2388 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2389 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2390 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2391 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2392 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2393 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2394 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2395 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2396 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2397 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2398 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2399 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2400 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2401 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2402 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2403 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2404 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2405 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2406 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2407 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2408 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2409 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2410 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2411 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2412 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2413 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2414 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2415 
2416 /******************* Bit definition for CAN_F12R1 register ******************/
2417 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2418 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2419 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2420 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2421 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2422 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2423 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2424 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2425 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2426 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2427 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2428 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2429 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2430 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2431 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2432 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2433 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2434 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2435 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2436 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2437 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2438 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2439 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2440 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2441 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2442 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2443 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2444 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2445 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2446 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2447 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2448 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2449 
2450 /******************* Bit definition for CAN_F13R1 register ******************/
2451 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2452 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2453 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2454 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2455 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2456 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2457 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2458 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2459 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2460 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2461 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2462 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2463 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2464 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2465 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2466 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2467 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2468 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2469 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2470 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2471 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2472 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2473 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2474 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2475 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2476 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2477 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2478 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2479 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2480 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2481 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2482 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2483 
2484 /******************* Bit definition for CAN_F0R2 register *******************/
2485 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2486 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2487 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2488 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2489 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2490 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2491 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2492 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2493 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2494 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2495 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2496 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2497 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2498 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2499 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2500 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2501 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2502 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2503 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2504 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2505 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2506 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2507 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2508 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2509 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2510 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2511 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2512 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2513 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2514 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2515 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2516 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2517 
2518 /******************* Bit definition for CAN_F1R2 register *******************/
2519 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2520 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2521 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2522 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2523 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2524 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2525 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2526 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2527 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2528 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2529 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2530 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2531 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2532 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2533 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2534 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2535 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2536 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2537 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2538 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2539 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2540 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2541 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2542 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2543 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2544 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2545 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2546 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2547 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2548 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2549 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2550 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2551 
2552 /******************* Bit definition for CAN_F2R2 register *******************/
2553 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2554 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2555 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2556 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2557 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2558 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2559 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2560 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2561 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2562 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2563 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2564 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2565 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2566 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2567 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2568 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2569 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2570 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2571 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2572 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2573 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2574 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2575 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2576 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2577 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2578 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2579 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2580 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2581 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2582 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2583 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2584 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2585 
2586 /******************* Bit definition for CAN_F3R2 register *******************/
2587 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2588 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2589 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2590 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2591 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2592 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2593 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2594 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2595 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2596 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2597 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2598 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2599 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2600 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2601 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2602 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2603 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2604 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2605 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2606 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2607 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2608 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2609 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2610 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2611 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2612 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2613 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2614 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2615 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2616 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2617 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2618 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2619 
2620 /******************* Bit definition for CAN_F4R2 register *******************/
2621 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2622 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2623 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2624 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2625 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2626 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2627 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2628 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2629 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2630 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2631 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2632 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2633 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2634 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2635 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2636 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2637 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2638 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2639 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2640 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2641 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2642 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2643 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2644 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2645 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2646 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2647 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2648 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2649 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2650 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2651 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2652 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2653 
2654 /******************* Bit definition for CAN_F5R2 register *******************/
2655 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2656 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2657 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2658 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2659 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2660 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2661 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2662 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2663 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2664 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2665 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2666 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2667 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2668 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2669 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2670 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2671 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2672 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2673 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2674 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2675 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2676 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2677 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2678 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2679 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2680 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2681 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2682 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2683 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2684 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2685 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2686 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2687 
2688 /******************* Bit definition for CAN_F6R2 register *******************/
2689 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2690 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2691 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2692 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2693 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2694 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2695 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2696 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2697 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2698 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2699 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2700 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2701 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2702 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2703 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2704 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2705 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2706 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2707 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2708 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2709 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2710 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2711 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2712 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2713 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2714 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2715 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2716 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2717 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2718 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2719 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2720 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2721 
2722 /******************* Bit definition for CAN_F7R2 register *******************/
2723 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2724 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2725 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2726 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2727 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2728 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2729 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2730 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2731 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2732 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2733 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2734 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2735 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2736 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2737 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2738 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2739 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2740 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2741 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2742 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2743 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2744 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2745 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2746 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2747 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2748 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2749 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2750 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2751 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2752 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2753 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2754 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2755 
2756 /******************* Bit definition for CAN_F8R2 register *******************/
2757 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2758 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2759 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2760 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2761 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2762 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2763 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2764 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2765 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2766 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2767 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2768 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2769 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2770 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2771 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2772 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2773 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2774 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2775 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2776 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2777 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2778 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2779 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2780 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2781 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2782 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2783 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2784 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2785 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2786 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2787 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2788 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2789 
2790 /******************* Bit definition for CAN_F9R2 register *******************/
2791 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2792 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2793 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2794 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2795 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2796 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2797 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2798 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2799 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2800 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2801 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2802 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2803 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2804 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2805 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2806 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2807 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2808 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2809 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2810 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2811 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2812 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2813 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2814 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2815 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2816 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2817 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2818 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2819 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2820 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2821 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2822 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2823 
2824 /******************* Bit definition for CAN_F10R2 register ******************/
2825 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2826 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2827 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2828 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2829 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2830 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2831 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2832 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2833 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2834 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2835 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2836 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2837 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2838 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2839 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2840 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2841 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2842 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2843 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2844 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2845 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2846 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2847 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2848 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2849 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2850 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2851 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2852 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2853 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2854 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2855 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2856 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2857 
2858 /******************* Bit definition for CAN_F11R2 register ******************/
2859 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2860 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2861 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2862 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2863 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2864 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2865 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2866 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2867 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2868 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2869 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2870 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2871 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2872 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2873 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2874 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2875 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2876 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2877 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2878 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2879 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2880 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2881 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2882 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2883 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2884 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2885 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2886 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2887 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2888 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2889 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2890 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2891 
2892 /******************* Bit definition for CAN_F12R2 register ******************/
2893 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2894 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2895 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2896 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2897 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2898 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2899 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2900 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2901 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2902 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2903 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2904 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2905 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2906 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2907 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2908 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2909 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2910 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2911 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2912 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2913 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2914 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2915 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2916 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2917 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2918 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2919 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2920 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2921 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2922 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2923 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2924 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2925 
2926 /******************* Bit definition for CAN_F13R2 register ******************/
2927 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2928 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2929 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2930 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2931 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2932 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2933 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2934 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2935 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2936 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2937 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2938 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2939 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2940 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2941 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2942 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2943 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2944 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2945 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2946 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2947 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2948 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2949 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2950 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2951 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2952 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2953 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2954 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2955 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2956 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2957 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2958 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2959 
2960 /******************************************************************************/
2961 /* */
2962 /* CRC calculation unit */
2963 /* */
2964 /******************************************************************************/
2965 /******************* Bit definition for CRC_DR register *********************/
2966 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
2967 
2968 
2969 /******************* Bit definition for CRC_IDR register ********************/
2970 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
2971 
2972 
2973 /******************** Bit definition for CRC_CR register ********************/
2974 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
2975 
2976 /******************************************************************************/
2977 /* */
2978 /* Digital to Analog Converter */
2979 /* */
2980 /******************************************************************************/
2981 /******************** Bit definition for DAC_CR register ********************/
2982 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
2983 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
2984 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
2985 
2986 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2987 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
2988 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
2989 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
2990 
2991 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2992 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
2993 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
2994 
2995 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2996 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2997 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2998 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
2999 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3000 
3001 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
3002 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
3003 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
3004 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
3005 
3006 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3007 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
3008 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
3009 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
3010 
3011 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3012 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
3013 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
3014 
3015 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3016 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3017 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3018 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3019 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3020 
3021 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
3022 
3023 /***************** Bit definition for DAC_SWTRIGR register ******************/
3024 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
3025 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
3026 
3027 /***************** Bit definition for DAC_DHR12R1 register ******************/
3028 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
3029 
3030 /***************** Bit definition for DAC_DHR12L1 register ******************/
3031 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
3032 
3033 /****************** Bit definition for DAC_DHR8R1 register ******************/
3034 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
3035 
3036 /***************** Bit definition for DAC_DHR12R2 register ******************/
3037 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
3038 
3039 /***************** Bit definition for DAC_DHR12L2 register ******************/
3040 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
3041 
3042 /****************** Bit definition for DAC_DHR8R2 register ******************/
3043 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
3044 
3045 /***************** Bit definition for DAC_DHR12RD register ******************/
3046 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
3047 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
3048 
3049 /***************** Bit definition for DAC_DHR12LD register ******************/
3050 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
3051 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
3052 
3053 /****************** Bit definition for DAC_DHR8RD register ******************/
3054 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
3055 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
3056 
3057 /******************* Bit definition for DAC_DOR1 register *******************/
3058 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
3059 
3060 /******************* Bit definition for DAC_DOR2 register *******************/
3061 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
3062 
3063 /******************** Bit definition for DAC_SR register ********************/
3064 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
3065 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
3066 
3067 /******************************************************************************/
3068 /* */
3069 /* Debug MCU */
3070 /* */
3071 /******************************************************************************/
3072 
3073 /******************************************************************************/
3074 /* */
3075 /* DCMI */
3076 /* */
3077 /******************************************************************************/
3078 /******************** Bits definition for DCMI_CR register ******************/
3079 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3080 #define DCMI_CR_CM ((uint32_t)0x00000002)
3081 #define DCMI_CR_CROP ((uint32_t)0x00000004)
3082 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
3083 #define DCMI_CR_ESS ((uint32_t)0x00000010)
3084 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3085 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3086 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3087 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3088 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3089 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3090 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3091 #define DCMI_CR_CRE ((uint32_t)0x00001000)
3092 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3093 
3094 /******************** Bits definition for DCMI_SR register ******************/
3095 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3096 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3097 #define DCMI_SR_FNE ((uint32_t)0x00000004)
3098 
3099 /******************** Bits definition for DCMI_RISR register ****************/
3100 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3101 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3102 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3103 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3104 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3105 
3106 /******************** Bits definition for DCMI_IER register *****************/
3107 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3108 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3109 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3110 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3111 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3112 
3113 /******************** Bits definition for DCMI_MISR register ****************/
3114 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3115 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3116 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3117 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3118 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3119 
3120 /******************** Bits definition for DCMI_ICR register *****************/
3121 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3122 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3123 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3124 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3125 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3126 
3127 /******************************************************************************/
3128 /* */
3129 /* DMA Controller */
3130 /* */
3131 /******************************************************************************/
3132 /******************** Bits definition for DMA_SxCR register *****************/
3133 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3134 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3135 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3136 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3137 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3138 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3139 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3140 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3141 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3142 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3143 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
3144 #define DMA_SxCR_CT ((uint32_t)0x00080000)
3145 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
3146 #define DMA_SxCR_PL ((uint32_t)0x00030000)
3147 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3148 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3149 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3150 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3151 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3152 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3153 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3154 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3155 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3156 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
3157 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
3158 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3159 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3160 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3161 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3162 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3163 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3164 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3165 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3166 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3167 #define DMA_SxCR_EN ((uint32_t)0x00000001)
3168 
3169 /******************** Bits definition for DMA_SxCNDTR register **************/
3170 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
3171 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
3172 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
3173 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
3174 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
3175 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
3176 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
3177 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
3178 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
3179 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
3180 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
3181 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
3182 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
3183 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
3184 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
3185 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
3186 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
3187 
3188 /******************** Bits definition for DMA_SxFCR register ****************/
3189 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3190 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
3191 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3192 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3193 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3194 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3195 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3196 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3197 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3198 
3199 /******************** Bits definition for DMA_LISR register *****************/
3200 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3201 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3202 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3203 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3204 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3205 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3206 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3207 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3208 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3209 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3210 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3211 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3212 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3213 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3214 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3215 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3216 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3217 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3218 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3219 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3220 
3221 /******************** Bits definition for DMA_HISR register *****************/
3222 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3223 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3224 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3225 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3226 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3227 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3228 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3229 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3230 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3231 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3232 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3233 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3234 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3235 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3236 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3237 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3238 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3239 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3240 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3241 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3242 
3243 /******************** Bits definition for DMA_LIFCR register ****************/
3244 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3245 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3246 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3247 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3248 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3249 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3250 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3251 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3252 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3253 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3254 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3255 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3256 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3257 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3258 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3259 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3260 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3261 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3262 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3263 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3264 
3265 /******************** Bits definition for DMA_HIFCR register ****************/
3266 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3267 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3268 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3269 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3270 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3271 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3272 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3273 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3274 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3275 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3276 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3277 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3278 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3279 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3280 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3281 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3282 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3283 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3284 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3285 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3286 
3287 
3288 /******************************************************************************/
3289 /* */
3290 /* AHB Master DMA2D Controller (DMA2D) */
3291 /* */
3292 /******************************************************************************/
3293 
3294 /******************** Bit definition for DMA2D_CR register ******************/
3295 
3296 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
3297 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
3298 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
3299 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
3300 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
3301 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
3302 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
3303 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
3304 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
3305 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
3306 
3307 /******************** Bit definition for DMA2D_ISR register *****************/
3308 
3309 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
3310 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
3311 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
3312 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
3313 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
3314 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
3315 
3316 /******************** Bit definition for DMA2D_IFSR register ****************/
3317 
3318 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
3319 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
3320 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
3321 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
3322 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
3323 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
3324 
3325 /******************** Bit definition for DMA2D_FGMAR register ***************/
3326 
3327 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3328 
3329 /******************** Bit definition for DMA2D_FGOR register ****************/
3330 
3331 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3332 
3333 /******************** Bit definition for DMA2D_BGMAR register ***************/
3334 
3335 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3336 
3337 /******************** Bit definition for DMA2D_BGOR register ****************/
3338 
3339 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3340 
3341 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3342 
3343 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3344 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3345 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3346 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3347 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
3348 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3349 
3350 /******************** Bit definition for DMA2D_FGCOLR register **************/
3351 
3352 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3353 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3354 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3355 
3356 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3357 
3358 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3359 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3360 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3361 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3362 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
3363 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3364 
3365 /******************** Bit definition for DMA2D_BGCOLR register **************/
3366 
3367 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3368 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3369 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3370 
3371 /******************** Bit definition for DMA2D_FGCMAR register **************/
3372 
3373 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3374 
3375 /******************** Bit definition for DMA2D_BGCMAR register **************/
3376 
3377 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3378 
3379 /******************** Bit definition for DMA2D_OPFCCR register **************/
3380 
3381 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
3382 
3383 /******************** Bit definition for DMA2D_OCOLR register ***************/
3384 
3385 /*!<Mode_ARGB8888/RGB888 */
3386 
3387 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
3388 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
3389 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
3390 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
3391 
3392 /*!<Mode_RGB565 */
3393 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
3394 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
3395 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
3396 
3397 /*!<Mode_ARGB1555 */
3398 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
3399 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
3400 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
3401 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
3402 
3403 /*!<Mode_ARGB4444 */
3404 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
3405 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
3406 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
3407 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
3408 
3409 /******************** Bit definition for DMA2D_OMAR register ****************/
3410 
3411 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3412 
3413 /******************** Bit definition for DMA2D_OOR register *****************/
3414 
3415 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3416 
3417 /******************** Bit definition for DMA2D_NLR register *****************/
3418 
3419 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
3420 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
3421 
3422 /******************** Bit definition for DMA2D_LWR register *****************/
3423 
3424 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
3425 
3426 /******************** Bit definition for DMA2D_AMTCR register ***************/
3427 
3428 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
3429 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
3430 
3431 
3432 /******************** Bit definition for DMA2D_FGCLUT register **************/
3433 
3434 /******************** Bit definition for DMA2D_BGCLUT register **************/
3435 
3436 
3437 
3438 /******************************************************************************/
3439 /* */
3440 /* External Interrupt/Event Controller */
3441 /* */
3442 /******************************************************************************/
3443 /******************* Bit definition for EXTI_IMR register *******************/
3444 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3445 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3446 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3447 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3448 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3449 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3450 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3451 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3452 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3453 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3454 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3455 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3456 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3457 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3458 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3459 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3460 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3461 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3462 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3463 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3464 
3465 /******************* Bit definition for EXTI_EMR register *******************/
3466 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3467 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3468 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3469 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3470 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3471 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3472 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3473 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3474 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3475 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3476 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3477 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3478 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3479 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3480 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3481 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3482 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3483 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3484 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3485 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3486 
3487 /****************** Bit definition for EXTI_RTSR register *******************/
3488 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3489 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3490 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3491 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3492 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3493 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3494 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3495 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3496 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3497 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3498 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3499 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3500 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3501 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3502 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3503 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3504 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3505 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3506 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3507 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3508 
3509 /****************** Bit definition for EXTI_FTSR register *******************/
3510 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3511 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3512 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3513 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3514 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3515 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3516 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3517 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3518 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3519 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3520 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3521 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3522 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3523 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3524 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3525 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3526 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3527 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3528 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3529 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3530 
3531 /****************** Bit definition for EXTI_SWIER register ******************/
3532 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3533 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3534 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3535 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3536 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3537 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3538 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3539 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3540 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3541 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3542 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3543 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3544 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3545 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3546 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3547 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3548 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3549 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3550 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3551 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3552 
3553 /******************* Bit definition for EXTI_PR register ********************/
3554 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3555 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3556 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3557 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3558 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3559 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3560 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3561 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3562 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3563 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3564 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3565 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3566 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3567 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3568 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3569 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3570 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3571 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3572 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3573 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3574 
3575 /******************************************************************************/
3576 /* */
3577 /* FLASH */
3578 /* */
3579 /******************************************************************************/
3580 /******************* Bits definition for FLASH_ACR register *****************/
3581 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
3582 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3583 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3584 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3585 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3586 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3587 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3588 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3589 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3590 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
3591 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
3592 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
3593 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
3594 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
3595 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
3596 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
3597 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
3598 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3599 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
3600 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
3601 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
3602 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
3603 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
3604 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
3605 
3606 /******************* Bits definition for FLASH_SR register ******************/
3607 #define FLASH_SR_EOP ((uint32_t)0x00000001)
3608 #define FLASH_SR_SOP ((uint32_t)0x00000002)
3609 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3610 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3611 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3612 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
3613 #define FLASH_SR_BSY ((uint32_t)0x00010000)
3614 
3615 /******************* Bits definition for FLASH_CR register ******************/
3616 #define FLASH_CR_PG ((uint32_t)0x00000001)
3617 #define FLASH_CR_SER ((uint32_t)0x00000002)
3618 #define FLASH_CR_MER ((uint32_t)0x00000004)
3619 #define FLASH_CR_MER1 FLASH_CR_MER
3620 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
3621 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3622 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3623 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3624 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3625 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
3626 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
3627 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3628 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3629 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
3630 #define FLASH_CR_STRT ((uint32_t)0x00010000)
3631 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3632 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
3633 
3634 /******************* Bits definition for FLASH_OPTCR register ***************/
3635 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3636 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3637 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3638 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3639 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3640 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
3641 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
3642 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3643 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3644 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
3645 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3646 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3647 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3648 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3649 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3650 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3651 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3652 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3653 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
3654 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3655 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3656 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3657 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3658 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3659 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3660 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3661 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3662 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
3663 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
3664 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
3665 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
3666 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
3667 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
3668 
3669 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3670 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
3671 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
3672 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
3673 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
3674 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
3675 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
3676 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
3677 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
3678 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
3679 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
3680 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
3681 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
3682 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
3683 
3684 /******************************************************************************/
3685 /* */
3686 /* Flexible Memory Controller */
3687 /* */
3688 /******************************************************************************/
3689 /****************** Bit definition for FMC_BCR1 register *******************/
3690 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3691 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3692 
3693 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3694 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3695 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3696 
3697 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3698 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3699 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3700 
3701 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3702 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3703 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3704 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3705 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3706 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3707 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3708 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3709 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3710 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3711 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
3712 
3713 /****************** Bit definition for FMC_BCR2 register *******************/
3714 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3715 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3716 
3717 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3718 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3719 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3720 
3721 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3722 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3723 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3724 
3725 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3726 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3727 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3728 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3729 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3730 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3731 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3732 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3733 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3734 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3735 
3736 /****************** Bit definition for FMC_BCR3 register *******************/
3737 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3738 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3739 
3740 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3741 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3742 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3743 
3744 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3745 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3746 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3747 
3748 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3749 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3750 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3751 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3752 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3753 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3754 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3755 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3756 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3757 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3758 
3759 /****************** Bit definition for FMC_BCR4 register *******************/
3760 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3761 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3762 
3763 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3764 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3765 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3766 
3767 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3768 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3769 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3770 
3771 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3772 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3773 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3774 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3775 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3776 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3777 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3778 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3779 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3780 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3781 
3782 /****************** Bit definition for FMC_BTR1 register ******************/
3783 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3784 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3785 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3786 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3787 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3788 
3789 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3790 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3791 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3792 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3793 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3794 
3795 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3796 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3797 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3798 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3799 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3800 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3801 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3802 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3803 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3804 
3805 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3806 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3807 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3808 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3809 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3810 
3811 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3812 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3813 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3814 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3815 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3816 
3817 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3818 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3819 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3820 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3821 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3822 
3823 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3824 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3825 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3826 
3827 /****************** Bit definition for FMC_BTR2 register *******************/
3828 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3829 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3830 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3831 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3832 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3833 
3834 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3835 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3836 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3837 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3838 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3839 
3840 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3841 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3842 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3843 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3844 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3845 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3846 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3847 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3848 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3849 
3850 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3851 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3852 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3853 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3854 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3855 
3856 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3857 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3858 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3859 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3860 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3861 
3862 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3863 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3864 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3865 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3866 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3867 
3868 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3869 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3870 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3871 
3872 /******************* Bit definition for FMC_BTR3 register *******************/
3873 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3874 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3875 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3876 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3877 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3878 
3879 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3880 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3881 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3882 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3883 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3884 
3885 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3886 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3887 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3888 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3889 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3890 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3891 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3892 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3893 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3894 
3895 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3896 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3897 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3898 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3899 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3900 
3901 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3902 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3903 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3904 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3905 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3906 
3907 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3908 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3909 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3910 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3911 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3912 
3913 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3914 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3915 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3916 
3917 /****************** Bit definition for FMC_BTR4 register *******************/
3918 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3919 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3920 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3921 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3922 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3923 
3924 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3925 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3926 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3927 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3928 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3929 
3930 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3931 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3932 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3933 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3934 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3935 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3936 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3937 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3938 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3939 
3940 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3941 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3942 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3943 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3944 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3945 
3946 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3947 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3948 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3949 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3950 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3951 
3952 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3953 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3954 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3955 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3956 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3957 
3958 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3959 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3960 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3961 
3962 /****************** Bit definition for FMC_BWTR1 register ******************/
3963 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3964 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3965 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3966 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3967 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3968 
3969 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3970 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3971 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3972 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3973 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3974 
3975 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3976 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3977 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3978 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3979 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3980 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3981 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3982 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3983 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3984 
3985 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3986 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3987 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3988 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3989 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3990 
3991 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3992 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3993 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3994 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3995 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3996 
3997 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3998 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3999 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4000 
4001 /****************** Bit definition for FMC_BWTR2 register ******************/
4002 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4003 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4004 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4005 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4006 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4007 
4008 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4009 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4010 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4011 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4012 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4013 
4014 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4015 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4016 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4017 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4018 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4019 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4020 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4021 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4022 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4023 
4024 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4025 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4026 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
4027 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4028 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4029 
4030 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4031 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4032 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4033 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4034 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4035 
4036 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4037 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4038 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4039 
4040 /****************** Bit definition for FMC_BWTR3 register ******************/
4041 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4042 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4043 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4044 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4045 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4046 
4047 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4048 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4049 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4050 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4051 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4052 
4053 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4054 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4055 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4056 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4057 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4058 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4059 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4060 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4061 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4062 
4063 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4064 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4065 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4066 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4067 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4068 
4069 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4070 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4071 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4072 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4073 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4074 
4075 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4076 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4077 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4078 
4079 /****************** Bit definition for FMC_BWTR4 register ******************/
4080 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4081 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4082 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4083 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4084 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4085 
4086 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4087 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4088 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4089 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4090 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4091 
4092 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4093 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4094 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4095 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4096 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4097 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4098 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4099 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4100 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4101 
4102 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4103 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4104 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4105 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4106 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4107 
4108 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4109 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4110 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4111 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4112 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4113 
4114 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4115 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4116 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4117 
4118 /****************** Bit definition for FMC_PCR2 register *******************/
4119 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4120 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4121 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4122 
4123 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4124 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4125 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4126 
4127 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4128 
4129 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4130 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4131 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4132 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4133 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4134 
4135 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4136 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4137 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4138 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4139 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4140 
4141 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
4142 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4143 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4144 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4145 
4146 /****************** Bit definition for FMC_PCR3 register *******************/
4147 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4148 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4149 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4150 
4151 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4152 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4153 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4154 
4155 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4156 
4157 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4158 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4159 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4160 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4161 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4162 
4163 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4164 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4165 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4166 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4167 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4168 
4169 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4170 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4171 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4172 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4173 
4174 /****************** Bit definition for FMC_PCR4 register *******************/
4175 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4176 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4177 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4178 
4179 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4180 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4181 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4182 
4183 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4184 
4185 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4186 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4187 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4188 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4189 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4190 
4191 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4192 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4193 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4194 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4195 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4196 
4197 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4198 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4199 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4200 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4201 
4202 /******************* Bit definition for FMC_SR2 register *******************/
4203 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4204 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4205 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4206 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4207 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4208 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4209 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4210 
4211 /******************* Bit definition for FMC_SR3 register *******************/
4212 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4213 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4214 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4215 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4216 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4217 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4218 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4219 
4220 /******************* Bit definition for FMC_SR4 register *******************/
4221 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4222 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4223 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4224 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4225 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4226 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4227 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4228 
4229 /****************** Bit definition for FMC_PMEM2 register ******************/
4230 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
4231 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4232 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4233 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4234 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4235 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4236 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4237 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4238 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4239 
4240 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4241 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4242 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4243 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4244 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4245 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4246 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4247 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4248 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4249 
4250 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4251 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4252 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4253 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4254 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4255 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4256 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4257 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4258 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4259 
4260 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4261 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4262 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4263 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4264 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4265 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4266 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4267 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4268 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4269 
4270 /****************** Bit definition for FMC_PMEM3 register ******************/
4271 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4272 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4273 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4274 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4275 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4276 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4277 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4278 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4279 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4280 
4281 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4282 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4283 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4284 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4285 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4286 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4287 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4288 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4289 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4290 
4291 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4292 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4293 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4294 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4295 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4296 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4297 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4298 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4299 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4300 
4301 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4302 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4303 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4304 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4305 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4306 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4307 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4308 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4309 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4310 
4311 /****************** Bit definition for FMC_PMEM4 register ******************/
4312 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4313 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4314 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4315 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4316 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4317 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4318 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4319 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4320 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4321 
4322 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4323 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4324 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4325 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4326 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4327 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4328 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4329 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4330 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4331 
4332 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4333 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4334 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4335 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4336 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4337 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4338 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4339 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4340 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4341 
4342 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4343 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4344 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4345 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4346 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4347 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4348 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4349 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4350 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4351 
4352 /****************** Bit definition for FMC_PATT2 register ******************/
4353 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4354 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4355 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4356 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4357 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4358 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4359 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4360 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4361 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4362 
4363 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4364 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4365 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4366 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4367 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4368 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4369 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4370 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4371 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4372 
4373 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4374 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4375 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4376 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4377 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4378 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4379 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4380 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4381 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4382 
4383 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4384 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4385 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4386 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4387 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4388 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4389 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4390 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4391 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4392 
4393 /****************** Bit definition for FMC_PATT3 register ******************/
4394 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4395 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4396 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4397 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4398 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4399 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4400 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4401 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4402 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4403 
4404 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4405 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4406 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4407 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4408 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4409 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4410 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4411 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4412 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4413 
4414 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4415 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4416 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4417 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4418 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4419 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4420 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4421 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4422 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4423 
4424 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4425 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4426 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4427 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4428 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4429 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4430 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4431 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4432 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4433 
4434 /****************** Bit definition for FMC_PATT4 register ******************/
4435 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4436 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4437 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4438 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4439 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4440 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4441 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4442 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4443 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4444 
4445 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4446 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4447 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4448 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4449 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4450 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4451 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4452 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4453 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4454 
4455 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4456 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4457 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4458 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4459 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4460 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4461 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4462 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4463 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4464 
4465 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4466 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4467 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4468 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4469 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4470 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4471 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4472 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4473 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4474 
4475 /****************** Bit definition for FMC_PIO4 register *******************/
4476 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4477 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4478 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4479 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4480 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4481 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4482 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4483 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4484 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4485 
4486 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4487 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4488 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4489 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4490 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4491 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4492 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4493 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4494 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4495 
4496 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4497 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4498 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4499 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4500 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4501 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4502 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4503 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4504 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4505 
4506 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4507 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4508 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4509 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4510 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4511 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4512 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4513 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4514 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4515 
4516 /****************** Bit definition for FMC_ECCR2 register ******************/
4517 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4518 
4519 /****************** Bit definition for FMC_ECCR3 register ******************/
4520 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4521 
4522 /****************** Bit definition for FMC_SDCR1 register ******************/
4523 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4524 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4525 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4526 
4527 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4528 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4529 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4530 
4531 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4532 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4533 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4534 
4535 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4536 
4537 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4538 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4539 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4540 
4541 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
4542 
4543 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
4544 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4545 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4546 
4547 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4548 
4549 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
4550 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4551 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4552 
4553 /****************** Bit definition for FMC_SDCR2 register ******************/
4554 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4555 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4556 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4557 
4558 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4559 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4560 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4561 
4562 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4563 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4564 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4565 
4566 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4567 
4568 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4569 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4570 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4571 
4572 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
4573 
4574 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
4575 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4576 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4577 
4578 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4579 
4580 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
4581 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4582 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4583 
4584 /****************** Bit definition for FMC_SDTR1 register ******************/
4585 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4586 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4587 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4588 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4589 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4590 
4591 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4592 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4593 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4594 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4595 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4596 
4597 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4598 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4599 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4600 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4601 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4602 
4603 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4604 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4605 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4606 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4607 
4608 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4609 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4610 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4611 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4612 
4613 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4614 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4615 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4616 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4617 
4618 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4619 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4620 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4621 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4622 
4623 /****************** Bit definition for FMC_SDTR2 register ******************/
4624 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4625 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4626 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4627 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4628 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4629 
4630 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4631 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4632 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4633 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4634 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4635 
4636 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4637 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4638 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4639 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4640 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4641 
4642 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4643 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4644 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4645 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4646 
4647 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4648 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4649 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4650 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4651 
4652 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4653 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4654 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4655 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4656 
4657 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4658 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4659 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4660 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4661 
4662 /****************** Bit definition for FMC_SDCMR register ******************/
4663 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
4664 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4665 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4666 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
4667 
4668 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
4669 
4670 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
4671 
4672 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
4673 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
4674 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
4675 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
4676 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
4677 
4678 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
4679 
4680 /****************** Bit definition for FMC_SDRTR register ******************/
4681 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
4682 
4683 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
4684 
4685 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
4686 
4687 /****************** Bit definition for FMC_SDSR register ******************/
4688 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
4689 
4690 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
4691 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
4692 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
4693 
4694 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
4695 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
4696 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
4697 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
4698 
4699 
4700 
4701 /******************************************************************************/
4702 /* */
4703 /* General Purpose I/O */
4704 /* */
4705 /******************************************************************************/
4706 /****************** Bits definition for GPIO_MODER register *****************/
4707 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4708 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4709 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4710 
4711 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4712 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4713 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4714 
4715 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4716 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4717 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4718 
4719 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4720 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4721 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4722 
4723 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4724 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4725 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4726 
4727 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4728 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4729 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4730 
4731 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4732 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4733 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4734 
4735 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4736 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4737 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4738 
4739 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4740 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4741 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4742 
4743 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4744 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4745 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4746 
4747 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4748 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4749 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4750 
4751 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4752 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4753 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4754 
4755 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4756 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4757 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4758 
4759 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4760 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4761 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4762 
4763 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4764 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4765 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4766 
4767 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4768 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4769 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4770 
4771 /****************** Bits definition for GPIO_OTYPER register ****************/
4772 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4773 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4774 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4775 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4776 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4777 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4778 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4779 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4780 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4781 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4782 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4783 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4784 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4785 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4786 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4787 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4788 
4789 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4790 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4791 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4792 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4793 
4794 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4795 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4796 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4797 
4798 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4799 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4800 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4801 
4802 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4803 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4804 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4805 
4806 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4807 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4808 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4809 
4810 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4811 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4812 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4813 
4814 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4815 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4816 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4817 
4818 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4819 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4820 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4821 
4822 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4823 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4824 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4825 
4826 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4827 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4828 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4829 
4830 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4831 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4832 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4833 
4834 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4835 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4836 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4837 
4838 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4839 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4840 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4841 
4842 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4843 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4844 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4845 
4846 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4847 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4848 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4849 
4850 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4851 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4852 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4853 
4854 /****************** Bits definition for GPIO_PUPDR register *****************/
4855 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4856 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4857 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4858 
4859 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4860 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4861 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4862 
4863 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4864 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4865 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4866 
4867 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4868 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4869 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4870 
4871 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4872 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4873 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4874 
4875 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4876 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4877 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4878 
4879 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4880 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4881 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4882 
4883 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4884 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4885 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4886 
4887 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4888 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4889 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4890 
4891 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4892 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4893 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4894 
4895 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4896 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4897 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4898 
4899 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4900 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4901 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4902 
4903 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4904 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4905 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4906 
4907 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4908 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4909 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4910 
4911 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4912 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4913 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4914 
4915 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4916 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4917 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4918 
4919 /****************** Bits definition for GPIO_IDR register *******************/
4920 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4921 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4922 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4923 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4924 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4925 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4926 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4927 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4928 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4929 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4930 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4931 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4932 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4933 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4934 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4935 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4936 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4937 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4938 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4939 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4940 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4941 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4942 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4943 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4944 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4945 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4946 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4947 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4948 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4949 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4950 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4951 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4952 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4953 
4954 /****************** Bits definition for GPIO_ODR register *******************/
4955 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4956 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4957 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4958 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4959 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4960 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4961 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4962 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4963 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4964 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4965 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4966 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4967 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4968 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4969 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4970 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4971 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4972 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4973 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4974 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4975 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4976 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4977 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4978 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4979 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4980 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4981 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4982 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4983 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4984 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4985 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4986 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4987 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4988 
4989 /****************** Bits definition for GPIO_BSRR register ******************/
4990 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4991 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4992 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4993 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4994 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4995 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4996 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4997 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4998 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4999 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
5000 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
5001 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
5002 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
5003 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
5004 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
5005 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
5006 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
5007 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
5008 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
5009 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
5010 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
5011 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
5012 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
5013 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
5014 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
5015 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
5016 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
5017 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
5018 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
5019 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
5020 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
5021 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
5022 
5023 /******************************************************************************/
5024 /* */
5025 /* Inter-integrated Circuit Interface */
5026 /* */
5027 /******************************************************************************/
5028 /******************* Bit definition for I2C_CR1 register ********************/
5029 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
5030 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
5031 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
5032 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
5033 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
5034 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
5035 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
5036 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
5037 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
5038 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
5039 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
5040 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
5041 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
5042 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
5043 
5044 /******************* Bit definition for I2C_CR2 register ********************/
5045 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
5046 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5047 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5048 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5049 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5050 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5051 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5052 
5053 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
5054 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
5055 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
5056 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
5057 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
5058 
5059 /******************* Bit definition for I2C_OAR1 register *******************/
5060 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
5061 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
5062 
5063 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
5064 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
5065 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
5066 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
5067 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
5068 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
5069 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
5070 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
5071 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
5072 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
5073 
5074 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
5075 
5076 /******************* Bit definition for I2C_OAR2 register *******************/
5077 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
5078 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
5079 
5080 /******************** Bit definition for I2C_DR register ********************/
5081 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
5082 
5083 /******************* Bit definition for I2C_SR1 register ********************/
5084 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
5085 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
5086 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
5087 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
5088 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
5089 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
5090 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
5091 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
5092 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
5093 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
5094 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
5095 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
5096 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
5097 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
5098 
5099 /******************* Bit definition for I2C_SR2 register ********************/
5100 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
5101 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
5102 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
5103 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
5104 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
5105 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
5106 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
5107 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
5108 
5109 /******************* Bit definition for I2C_CCR register ********************/
5110 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
5111 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
5112 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
5113 
5114 /****************** Bit definition for I2C_TRISE register *******************/
5115 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
5116 
5117 /****************** Bit definition for I2C_FLTR register *******************/
5118 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
5119 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
5120 
5121 /******************************************************************************/
5122 /* */
5123 /* Independent WATCHDOG */
5124 /* */
5125 /******************************************************************************/
5126 /******************* Bit definition for IWDG_KR register ********************/
5127 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
5128 
5129 /******************* Bit definition for IWDG_PR register ********************/
5130 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
5131 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
5132 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
5133 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
5134 
5135 /******************* Bit definition for IWDG_RLR register *******************/
5136 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
5137 
5138 /******************* Bit definition for IWDG_SR register ********************/
5139 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
5140 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
5141 
5142 
5143 /******************************************************************************/
5144 /* */
5145 /* LCD-TFT Display Controller (LTDC) */
5146 /* */
5147 /******************************************************************************/
5148 
5149 /******************** Bit definition for LTDC_SSCR register *****************/
5150 
5151 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
5152 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
5153 
5154 /******************** Bit definition for LTDC_BPCR register *****************/
5155 
5156 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
5157 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
5158 
5159 /******************** Bit definition for LTDC_AWCR register *****************/
5160 
5161 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
5162 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
5163 
5164 /******************** Bit definition for LTDC_TWCR register *****************/
5165 
5166 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
5167 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
5168 
5169 /******************** Bit definition for LTDC_GCR register ******************/
5170 
5171 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
5172 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
5173 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
5174 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
5175 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
5176 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
5177 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
5178 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
5179 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
5180 
5181 /******************** Bit definition for LTDC_SRCR register *****************/
5182 
5183 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
5184 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
5185 
5186 /******************** Bit definition for LTDC_BCCR register *****************/
5187 
5188 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
5189 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
5190 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
5191 
5192 /******************** Bit definition for LTDC_IER register ******************/
5193 
5194 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
5195 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
5196 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
5197 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
5198 
5199 /******************** Bit definition for LTDC_ISR register ******************/
5200 
5201 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
5202 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
5203 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
5204 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
5205 
5206 /******************** Bit definition for LTDC_ICR register ******************/
5207 
5208 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
5209 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
5210 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
5211 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
5212 
5213 /******************** Bit definition for LTDC_LIPCR register ****************/
5214 
5215 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
5216 
5217 /******************** Bit definition for LTDC_CPSR register *****************/
5218 
5219 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
5220 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
5221 
5222 /******************** Bit definition for LTDC_CDSR register *****************/
5223 
5224 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
5225 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
5226 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
5227 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
5228 
5229 /******************** Bit definition for LTDC_LxCR register *****************/
5230 
5231 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
5232 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
5233 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
5234 
5235 /******************** Bit definition for LTDC_LxWHPCR register **************/
5236 
5237 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
5238 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
5239 
5240 /******************** Bit definition for LTDC_LxWVPCR register **************/
5241 
5242 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
5243 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
5244 
5245 /******************** Bit definition for LTDC_LxCKCR register ***************/
5246 
5247 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
5248 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
5249 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
5250 
5251 /******************** Bit definition for LTDC_LxPFCR register ***************/
5252 
5253 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
5254 
5255 /******************** Bit definition for LTDC_LxCACR register ***************/
5256 
5257 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
5258 
5259 /******************** Bit definition for LTDC_LxDCCR register ***************/
5260 
5261 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
5262 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
5263 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
5264 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
5265 
5266 /******************** Bit definition for LTDC_LxBFCR register ***************/
5267 
5268 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
5269 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
5270 
5271 /******************** Bit definition for LTDC_LxCFBAR register **************/
5272 
5273 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
5274 
5275 /******************** Bit definition for LTDC_LxCFBLR register **************/
5276 
5277 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
5278 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
5279 
5280 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5281 
5282 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
5283 
5284 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5285 
5286 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
5287 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
5288 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
5289 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
5290 
5291 
5292 /******************************************************************************/
5293 /* */
5294 /* Power Control */
5295 /* */
5296 /******************************************************************************/
5297 /******************** Bit definition for PWR_CR register ********************/
5298 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
5299 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
5300 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
5301 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
5302 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
5303 
5304 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
5305 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
5306 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
5307 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
5308 
5309 /*!< PVD level configuration */
5310 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
5311 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
5312 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
5313 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
5314 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
5315 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
5316 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
5317 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
5318 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
5319 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
5320 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
5321 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
5322 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
5323 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5324 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5325 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5326 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
5327 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
5328 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
5329 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5330 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5331 
5332 /* Legacy define */
5333 #define PWR_CR_PMODE PWR_CR_VOS
5334 
5335 /******************* Bit definition for PWR_CSR register ********************/
5336 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
5337 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
5338 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
5339 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
5340 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
5341 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
5342 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
5343 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
5344 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
5345 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
5346 
5347 /* Legacy define */
5348 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5349 
5350 /******************************************************************************/
5351 /* */
5352 /* Reset and Clock Control */
5353 /* */
5354 /******************************************************************************/
5355 /******************** Bit definition for RCC_CR register ********************/
5356 #define RCC_CR_HSION ((uint32_t)0x00000001)
5357 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5358 
5359 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5360 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
5361 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
5362 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
5363 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
5364 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
5365 
5366 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5367 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
5368 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
5369 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
5370 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
5371 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
5372 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
5373 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
5374 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
5375 
5376 #define RCC_CR_HSEON ((uint32_t)0x00010000)
5377 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
5378 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5379 #define RCC_CR_CSSON ((uint32_t)0x00080000)
5380 #define RCC_CR_PLLON ((uint32_t)0x01000000)
5381 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5382 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
5383 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
5384 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
5385 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
5386 
5387 /******************** Bit definition for RCC_PLLCFGR register ***************/
5388 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
5389 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
5390 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
5391 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5392 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
5393 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
5394 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
5395 
5396 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
5397 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
5398 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
5399 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
5400 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
5401 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
5402 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
5403 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
5404 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
5405 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
5406 
5407 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
5408 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
5409 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
5410 
5411 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
5412 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
5413 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
5414 
5415 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
5416 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
5417 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5418 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
5419 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
5420 
5421 /******************** Bit definition for RCC_CFGR register ******************/
5422 /*!< SW configuration */
5423 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5424 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5425 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5426 
5427 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5428 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5429 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
5430 
5431 /*!< SWS configuration */
5432 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5433 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
5434 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5435 
5436 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5437 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5438 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5439 
5440 /*!< HPRE configuration */
5441 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5442 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5443 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5444 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5445 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5446 
5447 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5448 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5449 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5450 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5451 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5452 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5453 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5454 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5455 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5456 
5457 /*!< PPRE1 configuration */
5458 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
5459 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5460 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5461 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5462 
5463 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5464 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
5465 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
5466 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
5467 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
5468 
5469 /*!< PPRE2 configuration */
5470 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
5471 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
5472 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
5473 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
5474 
5475 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5476 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
5477 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
5478 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
5479 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
5480 
5481 /*!< RTCPRE configuration */
5482 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
5483 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
5484 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
5485 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
5486 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
5487 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
5488 
5489 /*!< MCO1 configuration */
5490 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
5491 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
5492 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
5493 
5494 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5495 
5496 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
5497 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
5498 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
5499 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
5500 
5501 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
5502 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
5503 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
5504 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
5505 
5506 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
5507 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
5508 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
5509 
5510 /******************** Bit definition for RCC_CIR register *******************/
5511 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
5512 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
5513 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
5514 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
5515 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
5516 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
5517 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
5518 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
5519 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
5520 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
5521 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
5522 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
5523 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
5524 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5525 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
5526 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
5527 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
5528 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
5529 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5530 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
5531 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
5532 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
5533 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
5534 
5535 /******************** Bit definition for RCC_AHB1RSTR register **************/
5536 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
5537 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
5538 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5539 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
5540 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
5541 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
5542 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
5543 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
5544 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
5545 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
5546 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
5547 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
5548 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
5549 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5550 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
5551 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
5552 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
5553 
5554 /******************** Bit definition for RCC_AHB2RSTR register **************/
5555 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
5556 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
5557 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5558 
5559 /******************** Bit definition for RCC_AHB3RSTR register **************/
5560 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
5561 
5562 /******************** Bit definition for RCC_APB1RSTR register **************/
5563 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5564 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5565 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5566 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5567 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5568 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5569 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5570 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5571 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
5572 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
5573 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5574 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5575 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5576 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
5577 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
5578 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
5579 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5580 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5581 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
5582 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5583 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
5584 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5585 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
5586 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
5587 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
5588 
5589 /******************** Bit definition for RCC_APB2RSTR register **************/
5590 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
5591 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
5592 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5593 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5594 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5595 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
5596 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
5597 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
5598 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
5599 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
5600 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
5601 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
5602 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
5603 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
5604 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
5605 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
5606 
5607 /* Old SPI1RST bit definition, maintained for legacy purpose */
5608 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5609 
5610 /******************** Bit definition for RCC_AHB1ENR register ***************/
5611 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5612 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5613 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5614 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5615 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5616 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5617 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5618 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5619 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5620 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
5621 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
5622 
5623 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5624 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5625 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
5626 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5627 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5628 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
5629 
5630 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5631 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5632 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5633 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5634 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5635 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5636 
5637 /******************** Bit definition for RCC_AHB2ENR register ***************/
5638 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5639 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5640 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5641 
5642 /******************** Bit definition for RCC_AHB3ENR register ***************/
5643 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
5644 
5645 /******************** Bit definition for RCC_APB1ENR register ***************/
5646 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5647 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5648 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5649 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5650 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5651 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5652 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5653 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5654 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5655 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5656 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5657 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5658 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5659 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5660 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5661 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5662 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5663 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5664 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5665 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5666 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5667 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5668 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5669 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
5670 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
5671 
5672 /******************** Bit definition for RCC_APB2ENR register ***************/
5673 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5674 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5675 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5676 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5677 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5678 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5679 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5680 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
5681 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5682 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
5683 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5684 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5685 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5686 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5687 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
5688 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
5689 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
5690 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
5691 
5692 /******************** Bit definition for RCC_AHB1LPENR register *************/
5693 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5694 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5695 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5696 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5697 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5698 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5699 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5700 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5701 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5702 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
5703 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
5704 
5705 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5706 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5707 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5708 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5709 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5710 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
5711 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5712 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5713 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
5714 
5715 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5716 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5717 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5718 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5719 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5720 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5721 
5722 /******************** Bit definition for RCC_AHB2LPENR register *************/
5723 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5724 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5725 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5726 
5727 /******************** Bit definition for RCC_AHB3LPENR register *************/
5728 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
5729 
5730 /******************** Bit definition for RCC_APB1LPENR register *************/
5731 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5732 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5733 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5734 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5735 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5736 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5737 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5738 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5739 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5740 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5741 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5742 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5743 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5744 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5745 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5746 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5747 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5748 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5749 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5750 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5751 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5752 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5753 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5754 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
5755 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
5756 
5757 /******************** Bit definition for RCC_APB2LPENR register *************/
5758 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5759 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5760 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5761 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5762 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5763 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
5764 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5765 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5766 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5767 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
5768 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5769 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5770 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5771 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5772 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
5773 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
5774 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
5775 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
5776 
5777 /******************** Bit definition for RCC_BDCR register ******************/
5778 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5779 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5780 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5781 
5782 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5783 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5784 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5785 
5786 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5787 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5788 
5789 /******************** Bit definition for RCC_CSR register *******************/
5790 #define RCC_CSR_LSION ((uint32_t)0x00000001)
5791 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5792 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
5793 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5794 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5795 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5796 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5797 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5798 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5799 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5800 
5801 /******************** Bit definition for RCC_SSCGR register *****************/
5802 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5803 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5804 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5805 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5806 
5807 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5808 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5809 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5810 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5811 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5812 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5813 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5814 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5815 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5816 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5817 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5818 
5819 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
5820 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
5821 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
5822 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
5823 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
5824 
5825 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5826 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5827 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5828 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5829 
5830 
5831 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5832 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
5833 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
5834 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
5835 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
5836 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
5837 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
5838 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
5839 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
5840 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
5841 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
5842 
5843 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
5844 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
5845 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
5846 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
5847 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
5848 
5849 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
5850 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
5851 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
5852 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
5853 
5854 /******************** Bit definition for RCC_DCKCFGR register ***************/
5855 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
5856 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
5857 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
5858 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
5859 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
5860 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
5861 
5862 
5863 /******************************************************************************/
5864 /* */
5865 /* RNG */
5866 /* */
5867 /******************************************************************************/
5868 /******************** Bits definition for RNG_CR register *******************/
5869 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
5870 #define RNG_CR_IE ((uint32_t)0x00000008)
5871 
5872 /******************** Bits definition for RNG_SR register *******************/
5873 #define RNG_SR_DRDY ((uint32_t)0x00000001)
5874 #define RNG_SR_CECS ((uint32_t)0x00000002)
5875 #define RNG_SR_SECS ((uint32_t)0x00000004)
5876 #define RNG_SR_CEIS ((uint32_t)0x00000020)
5877 #define RNG_SR_SEIS ((uint32_t)0x00000040)
5878 
5879 /******************************************************************************/
5880 /* */
5881 /* Real-Time Clock (RTC) */
5882 /* */
5883 /******************************************************************************/
5884 /******************** Bits definition for RTC_TR register *******************/
5885 #define RTC_TR_PM ((uint32_t)0x00400000)
5886 #define RTC_TR_HT ((uint32_t)0x00300000)
5887 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5888 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5889 #define RTC_TR_HU ((uint32_t)0x000F0000)
5890 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5891 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5892 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5893 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5894 #define RTC_TR_MNT ((uint32_t)0x00007000)
5895 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5896 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5897 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5898 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5899 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5900 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5901 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5902 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5903 #define RTC_TR_ST ((uint32_t)0x00000070)
5904 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5905 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5906 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5907 #define RTC_TR_SU ((uint32_t)0x0000000F)
5908 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5909 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5910 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5911 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5912 
5913 /******************** Bits definition for RTC_DR register *******************/
5914 #define RTC_DR_YT ((uint32_t)0x00F00000)
5915 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5916 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5917 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5918 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5919 #define RTC_DR_YU ((uint32_t)0x000F0000)
5920 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5921 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5922 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5923 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5924 #define RTC_DR_WDU ((uint32_t)0x0000E000)
5925 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5926 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5927 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5928 #define RTC_DR_MT ((uint32_t)0x00001000)
5929 #define RTC_DR_MU ((uint32_t)0x00000F00)
5930 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
5931 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
5932 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
5933 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
5934 #define RTC_DR_DT ((uint32_t)0x00000030)
5935 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
5936 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
5937 #define RTC_DR_DU ((uint32_t)0x0000000F)
5938 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
5939 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
5940 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
5941 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
5942 
5943 /******************** Bits definition for RTC_CR register *******************/
5944 #define RTC_CR_COE ((uint32_t)0x00800000)
5945 #define RTC_CR_OSEL ((uint32_t)0x00600000)
5946 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5947 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5948 #define RTC_CR_POL ((uint32_t)0x00100000)
5949 #define RTC_CR_COSEL ((uint32_t)0x00080000)
5950 #define RTC_CR_BCK ((uint32_t)0x00040000)
5951 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
5952 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
5953 #define RTC_CR_TSIE ((uint32_t)0x00008000)
5954 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
5955 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5956 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5957 #define RTC_CR_TSE ((uint32_t)0x00000800)
5958 #define RTC_CR_WUTE ((uint32_t)0x00000400)
5959 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
5960 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
5961 #define RTC_CR_DCE ((uint32_t)0x00000080)
5962 #define RTC_CR_FMT ((uint32_t)0x00000040)
5963 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
5964 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
5965 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5966 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5967 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5968 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5969 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5970 
5971 /******************** Bits definition for RTC_ISR register ******************/
5972 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
5973 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5974 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
5975 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5976 #define RTC_ISR_TSF ((uint32_t)0x00000800)
5977 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
5978 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5979 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5980 #define RTC_ISR_INIT ((uint32_t)0x00000080)
5981 #define RTC_ISR_INITF ((uint32_t)0x00000040)
5982 #define RTC_ISR_RSF ((uint32_t)0x00000020)
5983 #define RTC_ISR_INITS ((uint32_t)0x00000010)
5984 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
5985 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5986 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5987 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5988 
5989 /******************** Bits definition for RTC_PRER register *****************/
5990 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5991 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5992 
5993 /******************** Bits definition for RTC_WUTR register *****************/
5994 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5995 
5996 /******************** Bits definition for RTC_CALIBR register ***************/
5997 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5998 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5999 
6000 /******************** Bits definition for RTC_ALRMAR register ***************/
6001 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
6002 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
6003 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
6004 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
6005 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
6006 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
6007 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
6008 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
6009 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
6010 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
6011 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
6012 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
6013 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
6014 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
6015 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
6016 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
6017 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
6018 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
6019 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
6020 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
6021 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
6022 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
6023 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
6024 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
6025 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
6026 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
6027 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
6028 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
6029 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
6030 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
6031 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
6032 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
6033 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
6034 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
6035 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
6036 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
6037 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
6038 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
6039 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
6040 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
6041 
6042 /******************** Bits definition for RTC_ALRMBR register ***************/
6043 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
6044 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
6045 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
6046 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
6047 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
6048 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
6049 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
6050 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
6051 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
6052 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
6053 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
6054 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
6055 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
6056 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
6057 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
6058 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
6059 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
6060 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
6061 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
6062 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
6063 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
6064 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
6065 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
6066 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
6067 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
6068 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
6069 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
6070 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
6071 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
6072 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
6073 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
6074 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
6075 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
6076 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
6077 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
6078 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
6079 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
6080 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
6081 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
6082 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
6083 
6084 /******************** Bits definition for RTC_WPR register ******************/
6085 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
6086 
6087 /******************** Bits definition for RTC_SSR register ******************/
6088 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
6089 
6090 /******************** Bits definition for RTC_SHIFTR register ***************/
6091 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
6092 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
6093 
6094 /******************** Bits definition for RTC_TSTR register *****************/
6095 #define RTC_TSTR_PM ((uint32_t)0x00400000)
6096 #define RTC_TSTR_HT ((uint32_t)0x00300000)
6097 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
6098 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
6099 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
6100 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
6101 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
6102 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
6103 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
6104 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
6105 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
6106 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
6107 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
6108 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
6109 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
6110 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
6111 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
6112 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
6113 #define RTC_TSTR_ST ((uint32_t)0x00000070)
6114 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
6115 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
6116 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
6117 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
6118 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
6119 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
6120 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
6121 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
6122 
6123 /******************** Bits definition for RTC_TSDR register *****************/
6124 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
6125 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
6126 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
6127 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
6128 #define RTC_TSDR_MT ((uint32_t)0x00001000)
6129 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
6130 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
6131 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
6132 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
6133 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
6134 #define RTC_TSDR_DT ((uint32_t)0x00000030)
6135 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
6136 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
6137 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
6138 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
6139 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
6140 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
6141 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
6142 
6143 /******************** Bits definition for RTC_TSSSR register ****************/
6144 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
6145 
6146 /******************** Bits definition for RTC_CAL register *****************/
6147 #define RTC_CALR_CALP ((uint32_t)0x00008000)
6148 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
6149 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
6150 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
6151 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
6152 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
6153 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
6154 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
6155 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
6156 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
6157 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
6158 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
6159 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
6160 
6161 /******************** Bits definition for RTC_TAFCR register ****************/
6162 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
6163 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
6164 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
6165 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
6166 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
6167 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
6168 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
6169 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
6170 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
6171 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
6172 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
6173 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
6174 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
6175 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
6176 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
6177 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
6178 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
6179 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
6180 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
6181 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
6182 
6183 /******************** Bits definition for RTC_ALRMASSR register *************/
6184 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
6185 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
6186 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
6187 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
6188 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
6189 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
6190 
6191 /******************** Bits definition for RTC_ALRMBSSR register *************/
6192 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
6193 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
6194 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
6195 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
6196 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
6197 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
6198 
6199 /******************** Bits definition for RTC_BKP0R register ****************/
6200 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
6201 
6202 /******************** Bits definition for RTC_BKP1R register ****************/
6203 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
6204 
6205 /******************** Bits definition for RTC_BKP2R register ****************/
6206 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
6207 
6208 /******************** Bits definition for RTC_BKP3R register ****************/
6209 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
6210 
6211 /******************** Bits definition for RTC_BKP4R register ****************/
6212 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
6213 
6214 /******************** Bits definition for RTC_BKP5R register ****************/
6215 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
6216 
6217 /******************** Bits definition for RTC_BKP6R register ****************/
6218 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
6219 
6220 /******************** Bits definition for RTC_BKP7R register ****************/
6221 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
6222 
6223 /******************** Bits definition for RTC_BKP8R register ****************/
6224 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
6225 
6226 /******************** Bits definition for RTC_BKP9R register ****************/
6227 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
6228 
6229 /******************** Bits definition for RTC_BKP10R register ***************/
6230 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
6231 
6232 /******************** Bits definition for RTC_BKP11R register ***************/
6233 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
6234 
6235 /******************** Bits definition for RTC_BKP12R register ***************/
6236 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
6237 
6238 /******************** Bits definition for RTC_BKP13R register ***************/
6239 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
6240 
6241 /******************** Bits definition for RTC_BKP14R register ***************/
6242 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
6243 
6244 /******************** Bits definition for RTC_BKP15R register ***************/
6245 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
6246 
6247 /******************** Bits definition for RTC_BKP16R register ***************/
6248 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
6249 
6250 /******************** Bits definition for RTC_BKP17R register ***************/
6251 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
6252 
6253 /******************** Bits definition for RTC_BKP18R register ***************/
6254 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
6255 
6256 /******************** Bits definition for RTC_BKP19R register ***************/
6257 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
6258 
6259 /******************************************************************************/
6260 /* */
6261 /* Serial Audio Interface */
6262 /* */
6263 /******************************************************************************/
6264 /******************** Bit definition for SAI_GCR register *******************/
6265 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6266 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6267 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6268 
6269 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6270 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6271 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6272 
6273 /******************* Bit definition for SAI_xCR1 register *******************/
6274 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
6275 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6276 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6277 
6278 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6279 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
6280 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
6281 
6282 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
6283 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
6284 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
6285 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
6286 
6287 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
6288 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
6289 
6290 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
6291 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6292 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6293 
6294 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
6295 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
6296 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
6297 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
6298 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
6299 
6300 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
6301 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
6302 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
6303 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
6304 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
6305 
6306 /******************* Bit definition for SAI_xCR2 register *******************/
6307 #define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
6308 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6309 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6310 
6311 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
6312 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
6313 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
6314 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
6315 
6316 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
6317 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
6318 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
6319 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
6320 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
6321 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
6322 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
6323 
6324 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
6325 
6326 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
6327 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
6328 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
6329 
6330 /****************** Bit definition for SAI_xFRCR register *******************/
6331 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
6332 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6333 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6334 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6335 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6336 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6337 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
6338 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
6339 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
6340 
6341 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
6342 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6343 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6344 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6345 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6346 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
6347 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
6348 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
6349 
6350 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
6351 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
6352 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
6353 
6354 /****************** Bit definition for SAI_xSLOTR register *******************/
6355 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
6356 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6357 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6358 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6359 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6360 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6361 
6362 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
6363 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
6364 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
6365 
6366 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
6367 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6368 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6369 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6370 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6371 
6372 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
6373 
6374 /******************* Bit definition for SAI_xIMR register *******************/
6375 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
6376 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
6377 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
6378 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
6379 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
6380 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
6381 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
6382 
6383 /******************** Bit definition for SAI_xSR register *******************/
6384 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
6385 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
6386 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
6387 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
6388 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
6389 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
6390 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
6391 
6392 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
6393 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
6394 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
6395 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
6396 
6397 /****************** Bit definition for SAI_xCLRFR register ******************/
6398 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
6399 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
6400 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
6401 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
6402 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
6403 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
6404 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
6405 
6406 /****************** Bit definition for SAI_xDR register ******************/
6407 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
6408 
6409 
6410 /******************************************************************************/
6411 /* */
6412 /* SD host Interface */
6413 /* */
6414 /******************************************************************************/
6415 /****************** Bit definition for SDIO_POWER register ******************/
6416 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
6417 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
6418 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
6419 
6420 /****************** Bit definition for SDIO_CLKCR register ******************/
6421 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
6422 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
6423 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
6424 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
6425 
6426 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
6427 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
6428 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
6429 
6430 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
6431 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
6432 
6433 /******************* Bit definition for SDIO_ARG register *******************/
6434 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
6435 
6436 /******************* Bit definition for SDIO_CMD register *******************/
6437 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
6438 
6439 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
6440 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
6441 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
6442 
6443 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
6444 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
6445 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
6446 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
6447 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
6448 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
6449 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
6450 
6451 /***************** Bit definition for SDIO_RESPCMD register *****************/
6452 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
6453 
6454 /****************** Bit definition for SDIO_RESP0 register ******************/
6455 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6456 
6457 /****************** Bit definition for SDIO_RESP1 register ******************/
6458 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6459 
6460 /****************** Bit definition for SDIO_RESP2 register ******************/
6461 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6462 
6463 /****************** Bit definition for SDIO_RESP3 register ******************/
6464 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6465 
6466 /****************** Bit definition for SDIO_RESP4 register ******************/
6467 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6468 
6469 /****************** Bit definition for SDIO_DTIMER register *****************/
6470 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
6471 
6472 /****************** Bit definition for SDIO_DLEN register *******************/
6473 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
6474 
6475 /****************** Bit definition for SDIO_DCTRL register ******************/
6476 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
6477 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
6478 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
6479 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
6480 
6481 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
6482 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
6483 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
6484 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
6485 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
6486 
6487 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
6488 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
6489 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
6490 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
6491 
6492 /****************** Bit definition for SDIO_DCOUNT register *****************/
6493 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
6494 
6495 /****************** Bit definition for SDIO_STA register ********************/
6496 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
6497 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
6498 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
6499 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
6500 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
6501 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
6502 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
6503 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
6504 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
6505 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
6506 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
6507 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
6508 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
6509 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
6510 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
6511 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
6512 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
6513 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
6514 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
6515 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
6516 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
6517 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
6518 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
6519 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
6520 
6521 /******************* Bit definition for SDIO_ICR register *******************/
6522 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
6523 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
6524 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
6525 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
6526 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
6527 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
6528 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
6529 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
6530 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
6531 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
6532 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
6533 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
6534 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
6535 
6536 /****************** Bit definition for SDIO_MASK register *******************/
6537 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
6538 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
6539 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
6540 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
6541 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
6542 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
6543 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
6544 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
6545 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
6546 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
6547 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
6548 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
6549 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
6550 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
6551 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
6552 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
6553 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
6554 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
6555 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
6556 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
6557 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
6558 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
6559 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
6560 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
6561 
6562 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6563 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
6564 
6565 /****************** Bit definition for SDIO_FIFO register *******************/
6566 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
6567 
6568 /******************************************************************************/
6569 /* */
6570 /* Serial Peripheral Interface */
6571 /* */
6572 /******************************************************************************/
6573 /******************* Bit definition for SPI_CR1 register ********************/
6574 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
6575 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
6576 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
6577 
6578 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
6579 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
6580 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
6581 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
6582 
6583 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
6584 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
6585 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
6586 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
6587 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
6588 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
6589 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
6590 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
6591 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
6592 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
6593 
6594 /******************* Bit definition for SPI_CR2 register ********************/
6595 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
6596 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
6597 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
6598 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
6599 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
6600 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
6601 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
6602 
6603 /******************** Bit definition for SPI_SR register ********************/
6604 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
6605 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
6606 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
6607 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
6608 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
6609 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
6610 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
6611 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
6612 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
6613 
6614 /******************** Bit definition for SPI_DR register ********************/
6615 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
6616 
6617 /******************* Bit definition for SPI_CRCPR register ******************/
6618 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
6619 
6620 /****************** Bit definition for SPI_RXCRCR register ******************/
6621 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
6622 
6623 /****************** Bit definition for SPI_TXCRCR register ******************/
6624 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
6625 
6626 /****************** Bit definition for SPI_I2SCFGR register *****************/
6627 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
6628 
6629 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
6630 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
6631 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
6632 
6633 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
6634 
6635 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
6636 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6637 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6638 
6639 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
6640 
6641 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6642 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6643 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6644 
6645 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
6646 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
6647 
6648 /****************** Bit definition for SPI_I2SPR register *******************/
6649 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
6650 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
6651 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
6652 
6653 /******************************************************************************/
6654 /* */
6655 /* SYSCFG */
6656 /* */
6657 /******************************************************************************/
6658 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6659 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
6660 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
6661 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
6662 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
6663 
6664 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
6665 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
6666 
6667 /****************** Bit definition for SYSCFG_PMC register ******************/
6668 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
6669 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
6670 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
6671 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
6672 
6673 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
6674 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
6675 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
6676 
6677 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6678 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
6679 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
6680 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
6681 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
6682 /**
6683  * @brief EXTI0 configuration
6684  */
6685 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
6686 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
6687 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
6688 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
6689 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
6690 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
6691 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
6692 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
6693 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
6694 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
6695 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
6696 
6697 /**
6698  * @brief EXTI1 configuration
6699  */
6700 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
6701 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
6702 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
6703 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
6704 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
6705 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
6706 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
6707 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
6708 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
6709 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
6710 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
6711 
6712 
6713 /**
6714  * @brief EXTI2 configuration
6715  */
6716 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
6717 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
6718 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
6719 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
6720 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
6721 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
6722 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
6723 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
6724 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
6725 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
6726 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
6727 
6728 
6729 /**
6730  * @brief EXTI3 configuration
6731  */
6732 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
6733 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
6734 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
6735 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
6736 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
6737 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
6738 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
6739 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
6740 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
6741 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
6742 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
6743 
6744 
6745 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6746 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
6747 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
6748 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
6749 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
6750 /**
6751  * @brief EXTI4 configuration
6752  */
6753 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
6754 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
6755 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
6756 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
6757 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
6758 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
6759 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
6760 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
6761 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
6762 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
6763 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
6764 
6765 /**
6766  * @brief EXTI5 configuration
6767  */
6768 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
6769 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
6770 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
6771 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
6772 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
6773 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
6774 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
6775 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
6776 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
6777 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
6778 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
6779 
6780 /**
6781  * @brief EXTI6 configuration
6782  */
6783 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
6784 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
6785 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
6786 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
6787 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
6788 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
6789 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
6790 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
6791 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
6792 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
6793 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
6794 
6795 
6796 /**
6797  * @brief EXTI7 configuration
6798  */
6799 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
6800 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
6801 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
6802 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
6803 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
6804 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
6805 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
6806 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
6807 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
6808 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
6809 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
6810 
6811 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6812 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
6813 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
6814 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
6815 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
6816 
6817 /**
6818  * @brief EXTI8 configuration
6819  */
6820 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
6821 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
6822 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
6823 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
6824 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
6825 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
6826 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
6827 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
6828 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
6829 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
6830 
6831 /**
6832  * @brief EXTI9 configuration
6833  */
6834 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
6835 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
6836 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
6837 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
6838 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
6839 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
6840 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
6841 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
6842 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
6843 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
6844 
6845 
6846 /**
6847  * @brief EXTI10 configuration
6848  */
6849 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
6850 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
6851 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
6852 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
6853 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
6854 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
6855 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
6856 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
6857 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
6858 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
6859 
6860 
6861 /**
6862  * @brief EXTI11 configuration
6863  */
6864 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
6865 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
6866 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
6867 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
6868 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
6869 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
6870 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
6871 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
6872 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
6873 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
6874 
6875 
6876 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6877 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
6878 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
6879 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
6880 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
6881 /**
6882  * @brief EXTI12 configuration
6883  */
6884 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
6885 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
6886 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
6887 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
6888 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
6889 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
6890 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
6891 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
6892 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
6893 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
6894 
6895 
6896 /**
6897  * @brief EXTI13 configuration
6898  */
6899 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
6900 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
6901 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
6902 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
6903 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
6904 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
6905 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
6906 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
6907 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
6908 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
6909 
6910 
6911 /**
6912  * @brief EXTI14 configuration
6913  */
6914 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
6915 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
6916 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
6917 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
6918 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
6919 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
6920 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
6921 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
6922 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
6923 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
6924 
6925 
6926 /**
6927  * @brief EXTI15 configuration
6928  */
6929 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
6930 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
6931 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
6932 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
6933 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
6934 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
6935 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
6936 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
6937 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
6938 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
6939 
6940 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6941 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
6942 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
6943 
6944 /******************************************************************************/
6945 /* */
6946 /* TIM */
6947 /* */
6948 /******************************************************************************/
6949 /******************* Bit definition for TIM_CR1 register ********************/
6950 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
6951 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
6952 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
6953 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
6954 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
6955 
6956 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6957 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
6958 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
6959 
6960 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
6961 
6962 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
6963 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
6964 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
6965 
6966 /******************* Bit definition for TIM_CR2 register ********************/
6967 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
6968 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
6969 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
6970 
6971 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
6972 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6973 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6974 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6975 
6976 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
6977 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
6978 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
6979 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
6980 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
6981 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
6982 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
6983 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
6984 
6985 /******************* Bit definition for TIM_SMCR register *******************/
6986 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
6987 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
6988 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
6989 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
6990 
6991 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
6992 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6993 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6994 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6995 
6996 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
6997 
6998 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
6999 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
7000 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
7001 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
7002 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
7003 
7004 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
7005 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
7006 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
7007 
7008 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
7009 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
7010 
7011 /******************* Bit definition for TIM_DIER register *******************/
7012 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
7013 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
7014 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
7015 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
7016 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
7017 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
7018 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
7019 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
7020 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
7021 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
7022 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
7023 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
7024 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
7025 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
7026 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
7027 
7028 /******************** Bit definition for TIM_SR register ********************/
7029 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
7030 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
7031 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
7032 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
7033 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
7034 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
7035 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
7036 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
7037 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
7038 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
7039 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
7040 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
7041 
7042 /******************* Bit definition for TIM_EGR register ********************/
7043 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
7044 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
7045 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
7046 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
7047 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
7048 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
7049 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
7050 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
7051 
7052 /****************** Bit definition for TIM_CCMR1 register *******************/
7053 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7054 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
7055 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
7056 
7057 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
7058 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
7059 
7060 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7061 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
7062 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
7063 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
7064 
7065 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
7066 
7067 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7068 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
7069 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
7070 
7071 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
7072 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
7073 
7074 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7075 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
7076 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
7077 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
7078 
7079 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
7080 
7081 /*----------------------------------------------------------------------------*/
7082 
7083 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7084 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7085 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7086 
7087 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7088 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7089 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7090 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7091 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7092 
7093 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7094 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7095 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7096 
7097 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7098 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7099 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7100 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7101 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7102 
7103 /****************** Bit definition for TIM_CCMR2 register *******************/
7104 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7105 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
7106 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
7107 
7108 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
7109 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
7110 
7111 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7112 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
7113 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
7114 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
7115 
7116 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
7117 
7118 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7119 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
7120 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
7121 
7122 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
7123 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
7124 
7125 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7126 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
7127 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
7128 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
7129 
7130 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
7131 
7132 /*----------------------------------------------------------------------------*/
7133 
7134 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7135 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7136 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7137 
7138 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7139 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7140 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7141 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7142 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7143 
7144 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7145 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7146 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7147 
7148 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7149 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7150 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7151 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7152 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7153 
7154 /******************* Bit definition for TIM_CCER register *******************/
7155 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
7156 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
7157 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
7158 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
7159 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
7160 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
7161 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
7162 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
7163 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
7164 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
7165 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
7166 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
7167 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
7168 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
7169 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
7170 
7171 /******************* Bit definition for TIM_CNT register ********************/
7172 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
7173 
7174 /******************* Bit definition for TIM_PSC register ********************/
7175 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
7176 
7177 /******************* Bit definition for TIM_ARR register ********************/
7178 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
7179 
7180 /******************* Bit definition for TIM_RCR register ********************/
7181 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
7182 
7183 /******************* Bit definition for TIM_CCR1 register *******************/
7184 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
7185 
7186 /******************* Bit definition for TIM_CCR2 register *******************/
7187 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
7188 
7189 /******************* Bit definition for TIM_CCR3 register *******************/
7190 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
7191 
7192 /******************* Bit definition for TIM_CCR4 register *******************/
7193 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
7194 
7195 /******************* Bit definition for TIM_BDTR register *******************/
7196 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7197 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
7198 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
7199 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
7200 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
7201 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
7202 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
7203 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
7204 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
7205 
7206 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
7207 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
7208 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
7209 
7210 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
7211 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
7212 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
7213 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
7214 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
7215 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
7216 
7217 /******************* Bit definition for TIM_DCR register ********************/
7218 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
7219 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
7220 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
7221 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
7222 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
7223 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
7224 
7225 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
7226 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
7227 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
7228 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
7229 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
7230 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
7231 
7232 /******************* Bit definition for TIM_DMAR register *******************/
7233 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
7234 
7235 /******************* Bit definition for TIM_OR register *********************/
7236 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
7237 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
7238 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
7239 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
7240 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
7241 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
7242 
7243 
7244 /******************************************************************************/
7245 /* */
7246 /* Universal Synchronous Asynchronous Receiver Transmitter */
7247 /* */
7248 /******************************************************************************/
7249 /******************* Bit definition for USART_SR register *******************/
7250 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
7251 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
7252 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
7253 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
7254 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
7255 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
7256 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
7257 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
7258 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
7259 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
7260 
7261 /******************* Bit definition for USART_DR register *******************/
7262 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
7263 
7264 /****************** Bit definition for USART_BRR register *******************/
7265 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
7266 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
7267 
7268 /****************** Bit definition for USART_CR1 register *******************/
7269 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
7270 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
7271 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
7272 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
7273 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
7274 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
7275 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
7276 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
7277 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
7278 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
7279 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
7280 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
7281 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
7282 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
7283 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
7284 
7285 /****************** Bit definition for USART_CR2 register *******************/
7286 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
7287 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
7288 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
7289 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
7290 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
7291 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
7292 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
7293 
7294 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
7295 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
7296 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
7297 
7298 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
7299 
7300 /****************** Bit definition for USART_CR3 register *******************/
7301 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
7302 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
7303 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
7304 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
7305 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
7306 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
7307 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
7308 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
7309 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
7310 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
7311 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
7312 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
7313 
7314 /****************** Bit definition for USART_GTPR register ******************/
7315 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
7316 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
7317 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
7318 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
7319 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
7320 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
7321 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
7322 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
7323 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
7324 
7325 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
7326 
7327 /******************************************************************************/
7328 /* */
7329 /* Window WATCHDOG */
7330 /* */
7331 /******************************************************************************/
7332 /******************* Bit definition for WWDG_CR register ********************/
7333 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7334 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
7335 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
7336 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
7337 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
7338 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
7339 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
7340 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
7341 
7342 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
7343 
7344 /******************* Bit definition for WWDG_CFR register *******************/
7345 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
7346 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
7347 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
7348 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
7349 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
7350 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
7351 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
7352 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
7353 
7354 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
7355 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
7356 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
7357 
7358 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
7359 
7360 /******************* Bit definition for WWDG_SR register ********************/
7361 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
7362 
7363 
7364 /******************************************************************************/
7365 /* */
7366 /* DBG */
7367 /* */
7368 /******************************************************************************/
7369 /******************** Bit definition for DBGMCU_IDCODE register *************/
7370 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
7371 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
7372 
7373 /******************** Bit definition for DBGMCU_CR register *****************/
7374 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
7375 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
7376 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
7377 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
7378 
7379 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
7380 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
7381 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
7382 
7383 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7384 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
7385 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
7386 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
7387 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
7388 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
7389 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
7390 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
7391 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
7392 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
7393 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
7394 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
7395 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
7396 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
7397 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
7398 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
7399 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
7400 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
7401 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
7402 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
7403 
7404 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7405 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
7406 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
7407 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
7408 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
7409 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
7410 
7411 /******************************************************************************/
7412 /* */
7413 /* Ethernet MAC Registers bits definitions */
7414 /* */
7415 /******************************************************************************/
7416 /* Bit definition for Ethernet MAC Control Register register */
7417 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7418 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7419 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7420 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7421  #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7422  #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7423  #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7424  #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7425  #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7426  #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7427  #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7428 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7429 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7430 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7431 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7432 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7433 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7434 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7435 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7436 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7437  a transmission attempt during retries after a collision: 0 =< r <2^k */
7438  #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7439  #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7440  #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7441  #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7442 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7443 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7444 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7445 
7446 /* Bit definition for Ethernet MAC Frame Filter Register */
7447 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7448 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7449 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7450 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7451 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7452  #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7453  #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7454  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7455 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7456 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7457 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7458 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7459 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7460 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7461 
7462 /* Bit definition for Ethernet MAC Hash Table High Register */
7463 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7464 
7465 /* Bit definition for Ethernet MAC Hash Table Low Register */
7466 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7467 
7468 /* Bit definition for Ethernet MAC MII Address Register */
7469 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7470 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7471 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7472  #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7473  #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7474  #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7475  #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7476  #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7477 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7478 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7479 
7480 /* Bit definition for Ethernet MAC MII Data Register */
7481 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7482 
7483 /* Bit definition for Ethernet MAC Flow Control Register */
7484 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7485 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7486 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7487  #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7488  #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7489  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7490  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7491 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7492 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7493 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7494 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7495 
7496 /* Bit definition for Ethernet MAC VLAN Tag Register */
7497 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7498 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7499 
7500 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7501 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7502 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7503  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7504 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7505  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7506  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7507  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7508  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7509  RSVD - Filter1 Command - RSVD - Filter0 Command
7510  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7511  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7512  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7513 
7514 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7515 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7516 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7517 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7518 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7519 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7520 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7521 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7522 
7523 /* Bit definition for Ethernet MAC Status Register */
7524 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7525 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7526 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7527 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7528 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7529 
7530 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7531 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7532 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7533 
7534 /* Bit definition for Ethernet MAC Address0 High Register */
7535 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7536 
7537 /* Bit definition for Ethernet MAC Address0 Low Register */
7538 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7539 
7540 /* Bit definition for Ethernet MAC Address1 High Register */
7541 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
7542 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
7543 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7544  #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7545  #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7546  #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7547  #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7548  #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7549  #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7550 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7551 
7552 /* Bit definition for Ethernet MAC Address1 Low Register */
7553 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
7554 
7555 /* Bit definition for Ethernet MAC Address2 High Register */
7556 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
7557 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
7558 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7559  #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7560  #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7561  #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7562  #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7563  #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7564  #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7565 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7566 
7567 /* Bit definition for Ethernet MAC Address2 Low Register */
7568 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
7569 
7570 /* Bit definition for Ethernet MAC Address3 High Register */
7571 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
7572 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
7573 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7574  #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7575  #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7576  #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7577  #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7578  #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7579  #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7580 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
7581 
7582 /* Bit definition for Ethernet MAC Address3 Low Register */
7583 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
7584 
7585 /******************************************************************************/
7586 /* Ethernet MMC Registers bits definition */
7587 /******************************************************************************/
7588 
7589 /* Bit definition for Ethernet MMC Contol Register */
7590 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
7591 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
7592 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
7593 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
7594 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
7595 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
7596 
7597 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7598 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
7599 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
7600 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
7601 
7602 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7603 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
7604 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
7605 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
7606 
7607 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7608 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7609 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7610 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7611 
7612 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7613 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7614 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7615 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7616 
7617 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7618 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7619 
7620 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7621 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7622 
7623 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7624 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
7625 
7626 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7627 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
7628 
7629 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7630 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
7631 
7632 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7633 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
7634 
7635 /******************************************************************************/
7636 /* Ethernet PTP Registers bits definition */
7637 /******************************************************************************/
7638 
7639 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7640 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
7641 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
7642 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
7643 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
7644 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
7645 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
7646 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
7647 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
7648 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
7649 
7650 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
7651 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
7652 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
7653 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
7654 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
7655 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
7656 
7657 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7658 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
7659 
7660 /* Bit definition for Ethernet PTP Time Stamp High Register */
7661 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
7662 
7663 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7664 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
7665 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
7666 
7667 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7668 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
7669 
7670 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7671 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
7672 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
7673 
7674 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7675 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
7676 
7677 /* Bit definition for Ethernet PTP Target Time High Register */
7678 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
7679 
7680 /* Bit definition for Ethernet PTP Target Time Low Register */
7681 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
7682 
7683 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7684 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
7685 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
7686 
7687 /******************************************************************************/
7688 /* Ethernet DMA Registers bits definition */
7689 /******************************************************************************/
7690 
7691 /* Bit definition for Ethernet DMA Bus Mode Register */
7692 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
7693 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
7694 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
7695 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
7696  #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7697  #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7698  #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7699  #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7700  #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7701  #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7702  #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7703  #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7704  #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7705  #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7706  #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7707  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7708 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
7709 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7710  #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
7711  #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
7712  #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
7713  #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7714 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
7715  #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7716  #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7717  #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7718  #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7719  #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7720  #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7721  #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7722  #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7723  #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7724  #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7725  #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7726  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7727 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
7728 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
7729 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
7730 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
7731 
7732 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7733 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
7734 
7735 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7736 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
7737 
7738 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7739 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
7740 
7741 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7742 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
7743 
7744 /* Bit definition for Ethernet DMA Status Register */
7745 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
7746 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
7747 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
7748 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
7749  /* combination with EBS[2:0] for GetFlagStatus function */
7750  #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
7751  #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
7752  #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
7753 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
7754  #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
7755  #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
7756  #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
7757  #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
7758  #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
7759  #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
7760 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
7761  #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
7762  #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
7763  #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
7764  #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
7765  #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
7766  #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
7767 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
7768 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
7769 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
7770 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
7771 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
7772 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
7773 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
7774 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
7775 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
7776 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
7777 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
7778 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
7779 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
7780 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
7781 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
7782 
7783 /* Bit definition for Ethernet DMA Operation Mode Register */
7784 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
7785 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
7786 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
7787 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
7788 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
7789 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
7790  #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7791  #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7792  #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7793  #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7794  #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7795  #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7796  #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7797  #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7798 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
7799 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
7800 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
7801 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
7802  #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
7803  #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
7804  #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
7805  #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
7806 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
7807 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
7808 
7809 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7810 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
7811 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
7812 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
7813 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
7814 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
7815 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
7816 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
7817 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
7818 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
7819 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
7820 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
7821 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
7822 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
7823 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
7824 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
7825 
7826 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7827 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
7828 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
7829 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
7830 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
7831 
7832 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7833 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
7834 
7835 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7836 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
7837 
7838 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7839 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
7840 
7841 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7842 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
7843 
7844 /******************************************************************************/
7845 /* */
7846 /* USB_OTG */
7847 /* */
7848 /******************************************************************************/
7849 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
7850 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
7851 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
7852 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
7853 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
7854 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
7855 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
7856 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
7857 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
7858 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
7859 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
7860 
7861 /******************** Bit definition forUSB_OTG_HCFG register ********************/
7862 
7863 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
7864 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7865 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7866 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
7867 
7868 /******************** Bit definition forUSB_OTG_DCFG register ********************/
7869 
7870 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
7871 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7872 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7873 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
7874 
7875 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
7876 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7877 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7878 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7879 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
7880 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
7881 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
7882 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
7883 
7884 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
7885 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
7886 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
7887 
7888 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
7889 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
7890 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
7891 
7892 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
7893 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
7894 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
7895 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
7896 
7897 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
7898 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
7899 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
7900 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
7901 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
7902 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
7903 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
7904 
7905 /******************** Bit definition forUSB_OTG_DCTL register ********************/
7906 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
7907 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
7908 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
7909 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
7910 
7911 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
7912 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7913 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7914 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7915 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
7916 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
7917 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
7918 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
7919 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
7920 
7921 /******************** Bit definition forUSB_OTG_HFIR register ********************/
7922 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
7923 
7924 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
7925 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
7926 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
7927 
7928 /******************** Bit definition forUSB_OTG_DSTS register ********************/
7929 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
7930 
7931 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
7932 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
7933 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
7934 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
7935 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
7936 
7937 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
7938 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
7939 
7940 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
7941 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
7942 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
7943 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
7944 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
7945 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
7946 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
7947 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
7948 
7949 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
7950 
7951 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
7952 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7953 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7954 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7955 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
7956 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
7957 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
7958 
7959 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
7960 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
7961 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
7962 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
7963 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
7964 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
7965 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
7966 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
7967 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
7968 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
7969 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
7970 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
7971 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
7972 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
7973 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
7974 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
7975 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
7976 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
7977 
7978 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
7979 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
7980 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
7981 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
7982 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
7983 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
7984 
7985 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
7986 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7987 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7988 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
7989 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
7990 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
7991 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
7992 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
7993 
7994 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
7995 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
7996 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
7997 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
7998 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
7999 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8000 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8001 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8002 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8003 
8004 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
8005 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
8006 
8007 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
8008 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8009 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8010 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8011 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8012 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8013 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8014 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8015 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8016 
8017 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
8018 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8019 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8020 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8021 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8022 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8023 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8024 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8025 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
8026 
8027 /******************** Bit definition forUSB_OTG_HAINT register ********************/
8028 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
8029 
8030 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
8031 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8032 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8033 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
8034 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
8035 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
8036 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8037 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8038 
8039 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
8040 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
8041 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
8042 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
8043 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
8044 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
8045 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
8046 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
8047 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
8048 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
8049 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
8050 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
8051 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
8052 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
8053 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
8054 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
8055 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
8056 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
8057 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
8058 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
8059 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
8060 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
8061 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
8062 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
8063 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
8064 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
8065 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
8066 
8067 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
8068 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
8069 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
8070 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
8071 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
8072 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
8073 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
8074 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
8075 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
8076 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
8077 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
8078 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
8079 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
8080 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
8081 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
8082 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
8083 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
8084 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
8085 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
8086 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
8087 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
8088 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
8089 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
8090 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
8091 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
8092 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
8093 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
8094 
8095 /******************** Bit definition forUSB_OTG_DAINT register ********************/
8096 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
8097 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
8098 
8099 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
8100 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
8101 
8102 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8103 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
8104 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
8105 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
8106 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
8107 
8108 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
8109 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
8110 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
8111 
8112 /******************** Bit definition for OTG register ********************/
8113 
8114 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8115 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8116 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8117 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8118 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8119 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8120 
8121 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8122 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8123 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8124 
8125 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8126 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8127 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8128 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8129 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8130 
8131 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8132 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8133 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8134 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8135 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8136 
8137 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8138 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8139 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8140 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8141 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8142 
8143 /******************** Bit definition for OTG register ********************/
8144 
8145 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8146 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8147 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8148 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8149 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8150 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8151 
8152 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8153 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8154 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8155 
8156 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8157 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8158 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8159 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8160 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8161 
8162 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8163 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8164 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8165 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8166 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8167 
8168 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8169 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8170 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8171 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8172 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8173 
8174 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
8175 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
8176 
8177 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
8178 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
8179 
8180 /******************** Bit definition for OTG register ********************/
8181 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
8182 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
8183 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
8184 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
8185 
8186 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
8187 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
8188 
8189 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
8190 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
8191 
8192 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
8193 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8194 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8195 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8196 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8197 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8198 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8199 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8200 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8201 
8202 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
8203 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8204 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8205 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8206 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8207 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8208 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8209 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8210 
8211 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
8212 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
8213 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
8214 
8215 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
8216 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
8217 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
8218 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
8219 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
8220 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
8221 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
8222 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
8223 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
8224 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
8225 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
8226 
8227 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
8228 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8229 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8230 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8231 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8232 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
8233 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
8234 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
8235 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
8236 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
8237 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
8238 
8239 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
8240 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
8241 
8242 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
8243 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
8244 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
8245 
8246 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
8247 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
8248 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
8249 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
8250 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
8251 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
8252 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
8253 
8254 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
8255 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
8256 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
8257 
8258 /******************** Bit definition forUSB_OTG_CID register ********************/
8259 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
8260 
8261 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
8262 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8263 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8264 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
8265 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8266 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8267 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8268 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8269 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8270 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8271 
8272 /******************** Bit definition forUSB_OTG_HPRT register ********************/
8273 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
8274 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
8275 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
8276 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
8277 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
8278 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
8279 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
8280 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
8281 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
8282 
8283 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
8284 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
8285 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
8286 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
8287 
8288 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
8289 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
8290 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
8291 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
8292 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
8293 
8294 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
8295 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8296 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8297 
8298 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
8299 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8300 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8301 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
8302 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8303 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8304 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8305 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8306 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8307 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
8308 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8309 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
8310 
8311 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
8312 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
8313 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
8314 
8315 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
8316 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8317 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8318 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
8319 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8320 
8321 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8322 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8323 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8324 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8325 
8326 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
8327 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8328 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8329 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8330 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8331 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8332 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8333 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8334 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8335 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8336 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8337 
8338 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
8339 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8340 
8341 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
8342 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
8343 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
8344 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
8345 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
8346 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
8347 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
8348 
8349 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8350 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8351 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8352 
8353 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
8354 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
8355 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
8356 
8357 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
8358 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8359 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8360 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8361 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8362 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
8363 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
8364 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
8365 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
8366 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
8367 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
8368 
8369 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
8370 
8371 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
8372 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8373 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8374 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8375 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8376 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
8377 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
8378 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
8379 
8380 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
8381 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
8382 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
8383 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
8384 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
8385 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
8386 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
8387 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
8388 
8389 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
8390 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
8391 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
8392 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
8393 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
8394 
8395 /******************** Bit definition forUSB_OTG_HCINT register ********************/
8396 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
8397 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
8398 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8399 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
8400 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
8401 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
8402 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
8403 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
8404 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
8405 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
8406 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
8407 
8408 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
8409 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8410 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8411 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
8412 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
8413 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
8414 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
8415 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
8416 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
8417 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
8418 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
8419 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
8420 
8421 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
8422 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
8423 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
8424 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8425 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
8426 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
8427 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
8428 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
8429 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
8430 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
8431 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
8432 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
8433 
8434 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8435 
8436 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8437 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8438 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
8439 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
8440 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8441 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8442 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
8443 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
8444 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8445 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8446 
8447 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
8448 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8449 
8450 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
8451 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8452 
8453 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
8454 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
8455 
8456 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
8457 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
8458 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
8459 
8460 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
8461 
8462 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
8463 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8464 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8465 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8466 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8467 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8468 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8469 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8470 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
8471 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8472 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8473 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8474 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8475 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8476 
8477 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
8478 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8479 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8480 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
8481 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
8482 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
8483 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
8484 
8485 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
8486 
8487 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8488 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8489 
8490 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
8491 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8492 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8493 
8494 /******************** Bit definition for PCGCCTL register ********************/
8495 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
8496 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
8497 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
8498 
8499 
8500 /**
8501  * @}
8502  */
8503 
8504 /**
8505  * @}
8506  */
8507 
8508 /** @addtogroup Exported_macros
8509  * @{
8510  */
8511 
8512 /******************************* ADC Instances ********************************/
8513 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) ||
8514  ((INSTANCE) == ADC2) ||
8515  ((INSTANCE) == ADC3))
8516 
8517 /******************************* CAN Instances ********************************/
8518 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) ||
8519  ((INSTANCE) == CAN2))
8520 
8521 /******************************* CRC Instances ********************************/
8522 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8523 
8524 /******************************* DAC Instances ********************************/
8525 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
8526 
8527 /******************************* DCMI Instances *******************************/
8528 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
8529 
8530 /******************************* DMA2D Instances *******************************/
8531 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
8532 
8533 /******************************** DMA Instances *******************************/
8534 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) ||
8535  ((INSTANCE) == DMA1_Stream1) ||
8536  ((INSTANCE) == DMA1_Stream2) ||
8537  ((INSTANCE) == DMA1_Stream3) ||
8538  ((INSTANCE) == DMA1_Stream4) ||
8539  ((INSTANCE) == DMA1_Stream5) ||
8540  ((INSTANCE) == DMA1_Stream6) ||
8541  ((INSTANCE) == DMA1_Stream7) ||
8542  ((INSTANCE) == DMA2_Stream0) ||
8543  ((INSTANCE) == DMA2_Stream1) ||
8544  ((INSTANCE) == DMA2_Stream2) ||
8545  ((INSTANCE) == DMA2_Stream3) ||
8546  ((INSTANCE) == DMA2_Stream4) ||
8547  ((INSTANCE) == DMA2_Stream5) ||
8548  ((INSTANCE) == DMA2_Stream6) ||
8549  ((INSTANCE) == DMA2_Stream7))
8550 
8551 /******************************* GPIO Instances *******************************/
8552 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) ||
8553  ((INSTANCE) == GPIOB) ||
8554  ((INSTANCE) == GPIOC) ||
8555  ((INSTANCE) == GPIOD) ||
8556  ((INSTANCE) == GPIOE) ||
8557  ((INSTANCE) == GPIOF) ||
8558  ((INSTANCE) == GPIOG) ||
8559  ((INSTANCE) == GPIOH) ||
8560  ((INSTANCE) == GPIOI) ||
8561  ((INSTANCE) == GPIOJ) ||
8562  ((INSTANCE) == GPIOK))
8563 
8564 /******************************** I2C Instances *******************************/
8565 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) ||
8566  ((INSTANCE) == I2C2) ||
8567  ((INSTANCE) == I2C3))
8568 
8569 /******************************** I2S Instances *******************************/
8570 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) ||
8571  ((INSTANCE) == SPI3))
8572 
8573 /*************************** I2S Extended Instances ***************************/
8574 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) ||
8575  ((INSTANCE) == SPI3) ||
8576  ((INSTANCE) == I2S2ext) ||
8577  ((INSTANCE) == I2S3ext))
8578 
8579 /****************************** LTDC Instances ********************************/
8580 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
8581 
8582 /******************************* RNG Instances ********************************/
8583 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8584 
8585 /****************************** RTC Instances *********************************/
8586 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8587 
8588 /******************************* SAI Instances ********************************/
8589 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) ||
8590  ((PERIPH) == SAI1_Block_B))
8591 
8592 /******************************** SPI Instances *******************************/
8593 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) ||
8594  ((INSTANCE) == SPI2) ||
8595  ((INSTANCE) == SPI3) ||
8596  ((INSTANCE) == SPI4) ||
8597  ((INSTANCE) == SPI5) ||
8598  ((INSTANCE) == SPI6))
8599 
8600 /*************************** SPI Extended Instances ***************************/
8601 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) ||
8602  ((INSTANCE) == SPI2) ||
8603  ((INSTANCE) == SPI3) ||
8604  ((INSTANCE) == SPI4) ||
8605  ((INSTANCE) == SPI5) ||
8606  ((INSTANCE) == SPI6) ||
8607  ((INSTANCE) == I2S2ext) ||
8608  ((INSTANCE) == I2S3ext))
8609 
8610 /****************** TIM Instances : All supported instances *******************/
8611 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8612  ((INSTANCE) == TIM2) ||
8613  ((INSTANCE) == TIM3) ||
8614  ((INSTANCE) == TIM4) ||
8615  ((INSTANCE) == TIM5) ||
8616  ((INSTANCE) == TIM6) ||
8617  ((INSTANCE) == TIM7) ||
8618  ((INSTANCE) == TIM8) ||
8619  ((INSTANCE) == TIM9) ||
8620  ((INSTANCE) == TIM10) ||
8621  ((INSTANCE) == TIM11) ||
8622  ((INSTANCE) == TIM12) ||
8623  ((INSTANCE) == TIM13) ||
8624  ((INSTANCE) == TIM14))
8625 
8626 /************* TIM Instances : at least 1 capture/compare channel *************/
8627 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8628  ((INSTANCE) == TIM2) ||
8629  ((INSTANCE) == TIM3) ||
8630  ((INSTANCE) == TIM4) ||
8631  ((INSTANCE) == TIM5) ||
8632  ((INSTANCE) == TIM8) ||
8633  ((INSTANCE) == TIM9) ||
8634  ((INSTANCE) == TIM10) ||
8635  ((INSTANCE) == TIM11) ||
8636  ((INSTANCE) == TIM12) ||
8637  ((INSTANCE) == TIM13) ||
8638  ((INSTANCE) == TIM14))
8639 
8640 /************ TIM Instances : at least 2 capture/compare channels *************/
8641 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8642  ((INSTANCE) == TIM2) ||
8643  ((INSTANCE) == TIM3) ||
8644  ((INSTANCE) == TIM4) ||
8645  ((INSTANCE) == TIM5) ||
8646  ((INSTANCE) == TIM8) ||
8647  ((INSTANCE) == TIM9) ||
8648  ((INSTANCE) == TIM12))
8649 
8650 /************ TIM Instances : at least 3 capture/compare channels *************/
8651 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8652  ((INSTANCE) == TIM2) ||
8653  ((INSTANCE) == TIM3) ||
8654  ((INSTANCE) == TIM4) ||
8655  ((INSTANCE) == TIM5) ||
8656  ((INSTANCE) == TIM8))
8657 
8658 /************ TIM Instances : at least 4 capture/compare channels *************/
8659 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8660  ((INSTANCE) == TIM2) ||
8661  ((INSTANCE) == TIM3) ||
8662  ((INSTANCE) == TIM4) ||
8663  ((INSTANCE) == TIM5) ||
8664  ((INSTANCE) == TIM8))
8665 
8666 /******************** TIM Instances : Advanced-control timers *****************/
8667 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8668  ((INSTANCE) == TIM8))
8669 
8670 /******************* TIM Instances : Timer input XOR function *****************/
8671 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8672  ((INSTANCE) == TIM2) ||
8673  ((INSTANCE) == TIM3) ||
8674  ((INSTANCE) == TIM4) ||
8675  ((INSTANCE) == TIM5) ||
8676  ((INSTANCE) == TIM8))
8677 
8678 /****************** TIM Instances : DMA requests generation (UDE) *************/
8679 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8680  ((INSTANCE) == TIM2) ||
8681  ((INSTANCE) == TIM3) ||
8682  ((INSTANCE) == TIM4) ||
8683  ((INSTANCE) == TIM5) ||
8684  ((INSTANCE) == TIM6) ||
8685  ((INSTANCE) == TIM7) ||
8686  ((INSTANCE) == TIM8))
8687 
8688 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8689 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8690  ((INSTANCE) == TIM2) ||
8691  ((INSTANCE) == TIM3) ||
8692  ((INSTANCE) == TIM4) ||
8693  ((INSTANCE) == TIM5) ||
8694  ((INSTANCE) == TIM8))
8695 
8696 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8697 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8698  ((INSTANCE) == TIM2) ||
8699  ((INSTANCE) == TIM3) ||
8700  ((INSTANCE) == TIM4) ||
8701  ((INSTANCE) == TIM5) ||
8702  ((INSTANCE) == TIM8))
8703 
8704 /******************** TIM Instances : DMA burst feature ***********************/
8705 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8706  ((INSTANCE) == TIM2) ||
8707  ((INSTANCE) == TIM3) ||
8708  ((INSTANCE) == TIM4) ||
8709  ((INSTANCE) == TIM5) ||
8710  ((INSTANCE) == TIM8))
8711 
8712 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8713 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8714  ((INSTANCE) == TIM2) ||
8715  ((INSTANCE) == TIM3) ||
8716  ((INSTANCE) == TIM4) ||
8717  ((INSTANCE) == TIM5) ||
8718  ((INSTANCE) == TIM6) ||
8719  ((INSTANCE) == TIM7) ||
8720  ((INSTANCE) == TIM8) ||
8721  ((INSTANCE) == TIM9) ||
8722  ((INSTANCE) == TIM12))
8723 
8724 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8725 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8726  ((INSTANCE) == TIM2) ||
8727  ((INSTANCE) == TIM3) ||
8728  ((INSTANCE) == TIM4) ||
8729  ((INSTANCE) == TIM5) ||
8730  ((INSTANCE) == TIM8) ||
8731  ((INSTANCE) == TIM9) ||
8732  ((INSTANCE) == TIM12))
8733 
8734 /********************** TIM Instances : 32 bit Counter ************************/
8735 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) ||
8736  ((INSTANCE) == TIM5))
8737 
8738 /***************** TIM Instances : external trigger input availabe ************/
8739 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) ||
8740  ((INSTANCE) == TIM2) ||
8741  ((INSTANCE) == TIM3) ||
8742  ((INSTANCE) == TIM4) ||
8743  ((INSTANCE) == TIM5) ||
8744  ((INSTANCE) == TIM8))
8745 
8746 /****************** TIM Instances : remapping capability **********************/
8747 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) ||
8748  ((INSTANCE) == TIM5) ||
8749  ((INSTANCE) == TIM11))
8750 
8751 /******************* TIM Instances : output(s) available **********************/
8752 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)
8753  ((((INSTANCE) == TIM1) &&
8754  (((CHANNEL) == TIM_CHANNEL_1) ||
8755  ((CHANNEL) == TIM_CHANNEL_2) ||
8756  ((CHANNEL) == TIM_CHANNEL_3) ||
8757  ((CHANNEL) == TIM_CHANNEL_4)))
8758  ||
8759  (((INSTANCE) == TIM2) &&
8760  (((CHANNEL) == TIM_CHANNEL_1) ||
8761  ((CHANNEL) == TIM_CHANNEL_2) ||
8762  ((CHANNEL) == TIM_CHANNEL_3) ||
8763  ((CHANNEL) == TIM_CHANNEL_4)))
8764  ||
8765  (((INSTANCE) == TIM3) &&
8766  (((CHANNEL) == TIM_CHANNEL_1) ||
8767  ((CHANNEL) == TIM_CHANNEL_2) ||
8768  ((CHANNEL) == TIM_CHANNEL_3) ||
8769  ((CHANNEL) == TIM_CHANNEL_4)))
8770  ||
8771  (((INSTANCE) == TIM4) &&
8772  (((CHANNEL) == TIM_CHANNEL_1) ||
8773  ((CHANNEL) == TIM_CHANNEL_2) ||
8774  ((CHANNEL) == TIM_CHANNEL_3) ||
8775  ((CHANNEL) == TIM_CHANNEL_4)))
8776  ||
8777  (((INSTANCE) == TIM5) &&
8778  (((CHANNEL) == TIM_CHANNEL_1) ||
8779  ((CHANNEL) == TIM_CHANNEL_2) ||
8780  ((CHANNEL) == TIM_CHANNEL_3) ||
8781  ((CHANNEL) == TIM_CHANNEL_4)))
8782  ||
8783  (((INSTANCE) == TIM8) &&
8784  (((CHANNEL) == TIM_CHANNEL_1) ||
8785  ((CHANNEL) == TIM_CHANNEL_2) ||
8786  ((CHANNEL) == TIM_CHANNEL_3) ||
8787  ((CHANNEL) == TIM_CHANNEL_4)))
8788  ||
8789  (((INSTANCE) == TIM9) &&
8790  (((CHANNEL) == TIM_CHANNEL_1) ||
8791  ((CHANNEL) == TIM_CHANNEL_2)))
8792  ||
8793  (((INSTANCE) == TIM10) &&
8794  (((CHANNEL) == TIM_CHANNEL_1)))
8795  ||
8796  (((INSTANCE) == TIM11) &&
8797  (((CHANNEL) == TIM_CHANNEL_1)))
8798  ||
8799  (((INSTANCE) == TIM12) &&
8800  (((CHANNEL) == TIM_CHANNEL_1) ||
8801  ((CHANNEL) == TIM_CHANNEL_2)))
8802  ||
8803  (((INSTANCE) == TIM13) &&
8804  (((CHANNEL) == TIM_CHANNEL_1)))
8805  ||
8806  (((INSTANCE) == TIM14) &&
8807  (((CHANNEL) == TIM_CHANNEL_1))))
8808 
8809 /************ TIM Instances : complementary output(s) available ***************/
8810 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)
8811  ((((INSTANCE) == TIM1) &&
8812  (((CHANNEL) == TIM_CHANNEL_1) ||
8813  ((CHANNEL) == TIM_CHANNEL_2) ||
8814  ((CHANNEL) == TIM_CHANNEL_3)))
8815  ||
8816  (((INSTANCE) == TIM8) &&
8817  (((CHANNEL) == TIM_CHANNEL_1) ||
8818  ((CHANNEL) == TIM_CHANNEL_2) ||
8819  ((CHANNEL) == TIM_CHANNEL_3))))
8820 
8821 /******************** USART Instances : Synchronous mode **********************/
8822 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) ||
8823  ((INSTANCE) == USART2) ||
8824  ((INSTANCE) == USART3) ||
8825  ((INSTANCE) == USART6))
8826 
8827 /******************** UART Instances : Asynchronous mode **********************/
8828 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) ||
8829  ((INSTANCE) == USART2) ||
8830  ((INSTANCE) == USART3) ||
8831  ((INSTANCE) == UART4) ||
8832  ((INSTANCE) == UART5) ||
8833  ((INSTANCE) == USART6) ||
8834  ((INSTANCE) == UART7) ||
8835  ((INSTANCE) == UART8))
8836 
8837 /****************** UART Instances : Hardware Flow control ********************/
8838 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) ||
8839  ((INSTANCE) == USART2) ||
8840  ((INSTANCE) == USART3) ||
8841  ((INSTANCE) == USART6))
8842 
8843 /********************* UART Instances : Smard card mode ***********************/
8844 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) ||
8845  ((INSTANCE) == USART2) ||
8846  ((INSTANCE) == USART3) ||
8847  ((INSTANCE) == USART6))
8848 
8849 /*********************** UART Instances : IRDA mode ***************************/
8850 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) ||
8851  ((INSTANCE) == USART2) ||
8852  ((INSTANCE) == USART3) ||
8853  ((INSTANCE) == UART4) ||
8854  ((INSTANCE) == UART5) ||
8855  ((INSTANCE) == USART6) ||
8856  ((INSTANCE) == UART7) ||
8857  ((INSTANCE) == UART8))
8858 
8859 /****************************** IWDG Instances ********************************/
8860 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8861 
8862 /****************************** WWDG Instances ********************************/
8863 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8864 
8865 /**
8866  * @}
8867  */
8868 
8869 /**
8870  * @}
8871  */
8872 
8873 /**
8874  * @}
8875  */
8876 
8877 #ifdef __cplusplus
8878 }
8879 #endif /* __cplusplus */
8880 
8881 #endif /* __STM32F429xx_H */
8882 
8883 
8884 
8885 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ADC3
#define ADC3
Definition: stm32f4xx.h:1175
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:466
DMA1_Stream7_BASE
#define DMA1_Stream7_BASE
Definition: stm32f4xx.h:1102
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f4xx.h:395
IWDG
#define IWDG
Definition: stm32f4xx.h:1152
PVD_IRQn
Definition: stm32f429xx.h:97
TAMP_STAMP_IRQn
Definition: stm32f429xx.h:98
LTDC_Layer_TypeDef::CLUTWR
__IO uint32_t CLUTWR
Definition: stm32f429xx.h:694
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f429xx.h:998
GPIOK
#define GPIOK
Definition: stm32f429xx.h:1281
SAI1_Block_B_BASE
#define SAI1_Block_B_BASE
Definition: stm32f429xx.h:1134
TIM4
#define TIM4
Definition: stm32f4xx.h:1143
DBGMCU_APB1_FZ_DBG_IWDG_STOP
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP
Definition: stm32f4xx.h:6509
SPI3_IRQn
Definition: stm32f429xx.h:147
LTDC_IRQn
Definition: stm32f429xx.h:183
GPIO_ODR_ODR_7
#define GPIO_ODR_ODR_7
Definition: stm32f4xx.h:4505
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f429xx.h:141
DMA1_Stream6
#define DMA1_Stream6
Definition: stm32f4xx.h:1202
GPIOB_BASE
#define GPIOB_BASE
Definition: stm32f4xx.h:1083
DAC_BASE
#define DAC_BASE
Definition: stm32f4xx.h:1062
CAN_TypeDef::sTxMailBox
CAN_TxMailBox_TypeDef sTxMailBox[3]
Definition: stm32f4xx.h:388
USART6_BASE
#define USART6_BASE
Definition: stm32f4xx.h:1068
RCC_TypeDef::DCKCFGR
__IO uint32_t DCKCFGR
Definition: stm32f429xx.h:745
RCC_BASE
#define RCC_BASE
Definition: stm32f4xx.h:1092
DMA1_Stream5
#define DMA1_Stream5
Definition: stm32f4xx.h:1201
PWR_CR_VOS
#define PWR_CR_VOS
Definition: stm32f4xx.h:4751
GPIOI_BASE
#define GPIOI_BASE
Definition: stm32f4xx.h:1090
ETH_TypeDef::DMACHRBAR
__IO uint32_t DMACHRBAR
Definition: stm32f4xx.h:562
SPI4
#define SPI4
Definition: stm32f429xx.h:1256
OTG_HS_EP1_OUT_IRQn
Definition: stm32f429xx.h:170
FMC_Bank1_R_BASE
#define FMC_Bank1_R_BASE
Definition: stm32f429xx.h:1184
SPI2
#define SPI2
Definition: stm32f4xx.h:1154
USART6
#define USART6
Definition: stm32f4xx.h:1171
RTC_WKUP_IRQn
Definition: stm32f429xx.h:99
SPI4_BASE
#define SPI4_BASE
Definition: stm32f429xx.h:1124
GPIOG_BASE
#define GPIOG_BASE
Definition: stm32f4xx.h:1088
DebugMonitor_IRQn
Definition: stm32f429xx.h:92
TIM1
#define TIM1
Definition: stm32f4xx.h:1168
I2S2ext_BASE
#define I2S2ext_BASE
Definition: stm32f4xx.h:1048
FMC_Bank5_6_R_BASE
#define FMC_Bank5_6_R_BASE
Definition: stm32f429xx.h:1188
TIM13_BASE
#define TIM13_BASE
Definition: stm32f4xx.h:1043
DMA2_Stream1_BASE
#define DMA2_Stream1_BASE
Definition: stm32f4xx.h:1105
PendSV_IRQn
Definition: stm32f429xx.h:93
SPI1
#define SPI1
Definition: stm32f4xx.h:1177
GPIOA
#define GPIOA
Definition: stm32f4xx.h:1183
DMA1_Stream1_BASE
#define DMA1_Stream1_BASE
Definition: stm32f4xx.h:1096
SPI3
#define SPI3
Definition: stm32f4xx.h:1155
TIM6_DAC_IRQn
Definition: stm32f429xx.h:150
GPIO_IDR_IDR_14
#define GPIO_IDR_IDR_14
Definition: stm32f4xx.h:4477
TIM3
#define TIM3
Definition: stm32f4xx.h:1142
CAN2
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Definition: stm32f4xx.h:1165
IWDG_BASE
#define IWDG_BASE
Definition: stm32f4xx.h:1047
TIM12
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Definition: stm32f4xx.h:1147
GPIO_IDR_IDR_15
#define GPIO_IDR_IDR_15
Definition: stm32f4xx.h:4478
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__IO uint32_t TDHR
Definition: stm32f4xx.h:348
TIM3_BASE
#define TIM3_BASE
Definition: stm32f4xx.h:1037
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__IO uint32_t GTPR
Definition: stm32f429xx.h:904
DMA2D_TypeDef::BGCLUT
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Definition: stm32f429xx.h:417
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#define TIM9
Definition: stm32f4xx.h:1180
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Definition: stm32f4xx.h:4471
I2C2_EV_IRQn
Definition: stm32f429xx.h:129
GPIO_IDR_IDR_5
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Definition: stm32f4xx.h:4468
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#define TIM2
Definition: stm32f4xx.h:1141
DMA2_Stream0_BASE
#define DMA2_Stream0_BASE
Definition: stm32f4xx.h:1104
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Definition: stm32f4xx.h:1169
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Definition: stm32f429xx.h:151
DMA1_Stream6_IRQn
Definition: stm32f429xx.h:113
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f429xx.h:1031
PWR_CSR_VOSRDY
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#define GPIOB
Definition: stm32f4xx.h:1184
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Definition: stm32f4xx.h:1111
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Definition: stm32f429xx.h:173
GPIO_ODR_ODR_5
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Definition: stm32f4xx.h:4503
I2C1_EV_IRQn
Definition: stm32f429xx.h:127
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uint32_t Reserved40C
Definition: stm32f429xx.h:1028
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Definition: stm32f4xx.h:1189
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__IO uint32_t CDR
Definition: stm32f4xx.h:334
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Definition: stm32f429xx.h:158
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Definition: stm32f429xx.h:100
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Definition: stm32f429xx.h:166
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Definition: stm32f429xx.h:178
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__IO uint32_t CMPCR
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Definition: stm32f4xx.h:1153
GPIO_ODR_ODR_6
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Definition: stm32f4xx.h:4504
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Definition: stm32f429xx.h:1046
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Definition: stm32f429xx.h:135
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Definition: stm32f4xx.h:1086
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Definition: stm32f429xx.h:165
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Definition: stm32f429xx.h:152
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Definition: stm32f429xx.h:1280
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__IO uint32_t FIFO
Definition: stm32f4xx.h:842
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__IO uint32_t SDSR
Definition: stm32f429xx.h:586
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Definition: stm32f429xx.h:164
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#define TIM8_BASE
Definition: stm32f4xx.h:1066
EXTI15_10_IRQn
Definition: stm32f429xx.h:136
USB_OTG_GlobalTypeDef::DIEPTXF
__IO uint32_t DIEPTXF[0x0F]
Definition: stm32f429xx.h:953
GPIO_IDR_IDR_1
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Definition: stm32f4xx.h:4464
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Definition: stm32f429xx.h:104
GPIO_IDR_IDR_6
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Definition: stm32f4xx.h:4469
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Definition: stm32f429xx.h:118
DMA1_Stream2_BASE
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Definition: stm32f4xx.h:1097
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Definition: stm32f4xx.h:1038
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Definition: stm32f429xx.h:180
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Definition: stm32f4xx.h:1191
UsageFault_IRQn
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__IO uint32_t OR
Definition: stm32f429xx.h:889
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Definition: stm32f4xx.h:1051
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Definition: stm32f4xx.h:1112
DMA2_BASE
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Definition: stm32f4xx.h:1103
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Definition: stm32f429xx.h:1263
APB1PERIPH_BASE
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Definition: stm32f4xx.h:1030
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Definition: stm32f4xx.h:1107
DMA2_Stream3
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Definition: stm32f4xx.h:1208
AHB1PERIPH_BASE
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Definition: stm32f4xx.h:1032
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Definition: stm32f429xx.h:185
FMC_Bank2_3_TypeDef::RESERVED1
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Definition: stm32f429xx.h:553
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f4xx.h:447
RCC_TypeDef::RESERVED2
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Definition: stm32f4xx.h:751
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Definition: stm32f429xx.h:1262
DMA1_Stream3_BASE
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Definition: stm32f4xx.h:1098
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Definition: stm32f4xx.h:1089
HASH_RNG_IRQn
Definition: stm32f429xx.h:175
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Definition: stm32f4xx.h:1160
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Definition: stm32f429xx.h:1187
CRC_TypeDef::RESERVED0
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Definition: stm32f4xx.h:411
UART4_IRQn
Definition: stm32f429xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f429xx.h:171
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#define TIM12_BASE
Definition: stm32f4xx.h:1042
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Definition: stm32f429xx.h:156
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Definition: stm32f4xx.h:1052
DMA1_Stream0_BASE
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Definition: stm32f4xx.h:1095
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Definition: stm32f4xx.h:1054
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Definition: stm32f429xx.h:123
GPIOJ_BASE
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Definition: stm32f429xx.h:1149
ADC1_BASE
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Definition: stm32f4xx.h:1069
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f429xx.h:982
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Definition: stm32f4xx.h:1211
RNG_BASE
#define RNG_BASE
Definition: stm32f4xx.h:1122
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__IO uint32_t SR
Definition: stm32f4xx.h:945
SAI1_Block_B
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Definition: stm32f429xx.h:1266
TIM1_BASE
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Definition: stm32f4xx.h:1065
DMA1_Stream0
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Definition: stm32f4xx.h:1196
GPIO_ODR_ODR_0
#define GPIO_ODR_ODR_0
Definition: stm32f4xx.h:4498
CAN2_RX1_IRQn
Definition: stm32f429xx.h:161
UART7_IRQn
Definition: stm32f429xx.h:177
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Definition: stm32f4xx.h:1170
GPIO_ODR_ODR_1
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Definition: stm32f4xx.h:4499
SAI1_BASE
#define SAI1_BASE
Definition: stm32f429xx.h:1132
DMA1_Stream1
#define DMA1_Stream1
Definition: stm32f4xx.h:1197
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f4xx.h:794
SYSCFG_BASE
#define SYSCFG_BASE
Definition: stm32f4xx.h:1075
TIM9_BASE
#define TIM9_BASE
Definition: stm32f4xx.h:1077
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f4xx.h:370
FMC_Bank1_TypeDef::BTCR
__IO uint32_t BTCR[8]
Definition: stm32f429xx.h:529
TIM6
#define TIM6
Definition: stm32f4xx.h:1145
GPIOD
#define GPIOD
Definition: stm32f4xx.h:1186
GPIOH
#define GPIOH
Definition: stm32f4xx.h:1190
UART8
#define UART8
Definition: stm32f429xx.h:1245
CAN1_RX0_IRQn
Definition: stm32f429xx.h:116
I2C_TypeDef::FLTR
__IO uint32_t FLTR
Definition: stm32f429xx.h:635
GPIO_IDR_IDR_4
#define GPIO_IDR_IDR_4
Definition: stm32f4xx.h:4467
ETH_IRQn
Definition: stm32f429xx.h:157
TIM5
#define TIM5
Definition: stm32f4xx.h:1144
TIM4_IRQn
Definition: stm32f429xx.h:126
MemoryManagement_IRQn
Definition: stm32f429xx.h:88
SPI5_BASE
#define SPI5_BASE
Definition: stm32f429xx.h:1130
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f4xx.h:576
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f429xx.h:971
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:1000
GPIO_ODR_ODR_14
#define GPIO_ODR_ODR_14
Definition: stm32f4xx.h:4512
DMA2D
#define DMA2D
Definition: stm32f429xx.h:1304
RCC_IRQn
Definition: stm32f429xx.h:101
DMA1_Stream5_BASE
#define DMA1_Stream5_BASE
Definition: stm32f4xx.h:1100
TIM1_UP_TIM10_IRQn
Definition: stm32f429xx.h:121
LTDC_ER_IRQn
Definition: stm32f429xx.h:184
GPIO_ODR_ODR_12
#define GPIO_ODR_ODR_12
Definition: stm32f4xx.h:4510
DMA2_Stream7
#define DMA2_Stream7
Definition: stm32f4xx.h:1212
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f429xx.h:803
FLASH_R_BASE
#define FLASH_R_BASE
Definition: stm32f4xx.h:1093
GPIO_ODR_ODR_13
#define GPIO_ODR_ODR_13
Definition: stm32f4xx.h:4511
USART3_BASE
#define USART3_BASE
Definition: stm32f4xx.h:1053
LTDC_Layer1_BASE
#define LTDC_Layer1_BASE
Definition: stm32f429xx.h:1136
GPIO_IDR_IDR_3
#define GPIO_IDR_IDR_3
Definition: stm32f4xx.h:4466
CAN1
#define CAN1
Definition: stm32f4xx.h:1164
I2C2_BASE
#define I2C2_BASE
Definition: stm32f4xx.h:1057
GPIOC_BASE
#define GPIOC_BASE
Definition: stm32f4xx.h:1084
CAN1_TX_IRQn
Definition: stm32f429xx.h:115
DBGMCU_BASE
#define DBGMCU_BASE
Definition: stm32f4xx.h:1132
GPIO_IDR_IDR_13
#define GPIO_IDR_IDR_13
Definition: stm32f4xx.h:4476
DMA1_Stream2_IRQn
Definition: stm32f429xx.h:109
DMA1_Stream5_IRQn
Definition: stm32f429xx.h:112
GPIO_ODR_ODR_4
#define GPIO_ODR_ODR_4
Definition: stm32f4xx.h:4502
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f429xx.h:1010
TIM10
#define TIM10
Definition: stm32f4xx.h:1181
ADC2_BASE
#define ADC2_BASE
Definition: stm32f4xx.h:1070
SPI1_IRQn
Definition: stm32f429xx.h:131
SAI1_IRQn
Definition: stm32f429xx.h:182
FMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f429xx.h:573
ADC_IRQn
Definition: stm32f429xx.h:114
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32f429xx.h:815
APB2PERIPH_BASE
#define APB2PERIPH_BASE
Definition: stm32f4xx.h:1031
WWDG_BASE
#define WWDG_BASE
Definition: stm32f4xx.h:1046
DMA1_Stream6_BASE
#define DMA1_Stream6_BASE
Definition: stm32f4xx.h:1101
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f429xx.h:520
USB_OTG_OUTEndpointTypeDef::Reserved18
uint32_t Reserved18[2]
Definition: stm32f429xx.h:1015
GPIO_ODR_ODR_15
#define GPIO_ODR_ODR_15
Definition: stm32f4xx.h:4513
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f4xx.h:412
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f429xx.h:966
TIM8_CC_IRQn
Definition: stm32f429xx.h:142
GPIOF
#define GPIOF
Definition: stm32f4xx.h:1188
CAN2_BASE
#define CAN2_BASE
Definition: stm32f4xx.h:1060
DMA2_Stream5_BASE
#define DMA2_Stream5_BASE
Definition: stm32f4xx.h:1109
AHB2PERIPH_BASE
#define AHB2PERIPH_BASE
Definition: stm32f4xx.h:1033
SRAM1_BB_BASE
#define SRAM1_BB_BASE
Definition: stm32f4xx.h:1019
DMA2_Stream2
#define DMA2_Stream2
Definition: stm32f4xx.h:1207
DMA2_Stream5
#define DMA2_Stream5
Definition: stm32f4xx.h:1210
FMC_Bank2_3_R_BASE
#define FMC_Bank2_3_R_BASE
Definition: stm32f429xx.h:1186
EXTI0_IRQn
Definition: stm32f429xx.h:102
SPI1_BASE
#define SPI1_BASE
Definition: stm32f4xx.h:1074
DMA2_Stream1_IRQn
Definition: stm32f429xx.h:153
GPIOF_BASE
#define GPIOF_BASE
Definition: stm32f4xx.h:1087
LTDC_TypeDef::CDSR
__IO uint32_t CDSR
Definition: stm32f429xx.h:672
I2C2_ER_IRQn
Definition: stm32f429xx.h:130
DMA1_Stream7_IRQn
Definition: stm32f429xx.h:143
OTG_FS_WKUP_IRQn
Definition: stm32f429xx.h:138
DMA1_Stream2
#define DMA1_Stream2
Definition: stm32f4xx.h:1198
DMA2_Stream4_BASE
#define DMA2_Stream4_BASE
Definition: stm32f4xx.h:1108
I2C1_ER_IRQn
Definition: stm32f429xx.h:128
SPI6_IRQn
Definition: stm32f429xx.h:181
GPIOE
#define GPIOE
Definition: stm32f4xx.h:1187
TIM13
#define TIM13
Definition: stm32f4xx.h:1148
CRC
#define CRC
Definition: stm32f4xx.h:1192
DMA1_BASE
#define DMA1_BASE
Definition: stm32f4xx.h:1094
ADC_BASE
#define ADC_BASE
Definition: stm32f4xx.h:1072
DMA2_Stream2_IRQn
Definition: stm32f429xx.h:154
FLASH_CR_MER
#define FLASH_CR_MER
Definition: stm32f4xx.h:3398
USART1_BASE
#define USART1_BASE
Definition: stm32f4xx.h:1067
EXTI9_5_IRQn
Definition: stm32f429xx.h:119
BusFault_IRQn
Definition: stm32f429xx.h:89
DMA1_Stream4_BASE
#define DMA1_Stream4_BASE
Definition: stm32f4xx.h:1099
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f4xx.h:413
RTC_Alarm_IRQn
Definition: stm32f429xx.h:137
USART3
#define USART3
Definition: stm32f4xx.h:1158
USART2_IRQn
Definition: stm32f429xx.h:134
DMA1_Stream1_IRQn
Definition: stm32f429xx.h:108
GPIOA_BASE
#define GPIOA_BASE
Definition: stm32f4xx.h:1082
USB_OTG_HS_PERIPH_BASE
#define USB_OTG_HS_PERIPH_BASE
Definition: stm32f429xx.h:1194
DCMI
#define DCMI
Definition: stm32f4xx.h:1214
TIM11
#define TIM11
Definition: stm32f4xx.h:1182
UART7
#define UART7
Definition: stm32f429xx.h:1244
FPU_IRQn
Definition: stm32f429xx.h:176
DMA2_Stream3_IRQn
Definition: stm32f429xx.h:155
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f429xx.h:122
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f429xx.h:993
DMA1_Stream4
#define DMA1_Stream4
Definition: stm32f4xx.h:1200
CAN_TypeDef::sFilterRegister
CAN_FilterRegister_TypeDef sFilterRegister[28]
Definition: stm32f4xx.h:400
I2C1_BASE
#define I2C1_BASE
Definition: stm32f4xx.h:1056
TIM8_BRK_TIM12_IRQn
Definition: stm32f429xx.h:139
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f429xx.h:979
I2C3_ER_IRQn
Definition: stm32f429xx.h:169
GPIO_IDR_IDR_2
#define GPIO_IDR_IDR_2
Definition: stm32f4xx.h:4465
PERIPH_BASE
#define PERIPH_BASE
Definition: stm32f4xx.h:1014
GPIO_IDR_IDR_0
#define GPIO_IDR_IDR_0
Definition: stm32f4xx.h:4463
DMA2_Stream6_BASE
#define DMA2_Stream6_BASE
Definition: stm32f4xx.h:1110
GPIO_IDR_IDR_11
#define GPIO_IDR_IDR_11
Definition: stm32f4xx.h:4474
GPIO_ODR_ODR_3
#define GPIO_ODR_ODR_3
Definition: stm32f4xx.h:4501
EXTI1_IRQn
Definition: stm32f429xx.h:103
TIM1_BRK_TIM9_IRQn
Definition: stm32f429xx.h:120
DMA2D_BASE
#define DMA2D_BASE
Definition: stm32f429xx.h:1177
TIM3_IRQn
Definition: stm32f429xx.h:125
GPIO_ODR_ODR_2
#define GPIO_ODR_ODR_2
Definition: stm32f4xx.h:4500
DMA1_Stream0_IRQn
Definition: stm32f429xx.h:107
EXTI3_IRQn
Definition: stm32f429xx.h:105
DMA2_Stream1
#define DMA2_Stream1
Definition: stm32f4xx.h:1206
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f429xx.h:972
I2C2
#define I2C2
Definition: stm32f4xx.h:1162
TIM14_BASE
#define TIM14_BASE
Definition: stm32f4xx.h:1044
FMC_Bank1E_R_BASE
#define FMC_Bank1E_R_BASE
Definition: stm32f429xx.h:1185
CRC_BASE
#define CRC_BASE
Definition: stm32f4xx.h:1091
TIM2_BASE
#define TIM2_BASE
Definition: stm32f4xx.h:1036
TIM10_BASE
#define TIM10_BASE
Definition: stm32f4xx.h:1078
TIM8_UP_TIM13_IRQn
Definition: stm32f429xx.h:140
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f4xx.h:327
USART6_IRQn
Definition: stm32f429xx.h:167
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f4xx.h:488
SPI2_IRQn
Definition: stm32f429xx.h:132
USB_OTG_FS_PERIPH_BASE
#define USB_OTG_FS_PERIPH_BASE
Definition: stm32f429xx.h:1195
EXTI4_IRQn
Definition: stm32f429xx.h:106
TIM5_BASE
#define TIM5_BASE
Definition: stm32f4xx.h:1039
LTDC_Layer2_BASE
#define LTDC_Layer2_BASE
Definition: stm32f429xx.h:1137
GPIOD_BASE
#define GPIOD_BASE
Definition: stm32f4xx.h:1085
DMA1_Stream4_IRQn
Definition: stm32f429xx.h:111
SDIO_BASE
#define SDIO_BASE
Definition: stm32f4xx.h:1073
FMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f429xx.h:551
PWR_BASE
#define PWR_BASE
Definition: stm32f4xx.h:1061
GPIO_ODR_ODR_10
#define GPIO_ODR_ODR_10
Definition: stm32f4xx.h:4508
FMC_IRQn
Definition: stm32f429xx.h:144
TIM7_BASE
#define TIM7_BASE
Definition: stm32f4xx.h:1041
DAC
#define DAC
Definition: stm32f4xx.h:1167
ADC3_BASE
#define ADC3_BASE
Definition: stm32f4xx.h:1071
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f429xx.h:860
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f429xx.h:1012
OTG_FS_IRQn
Definition: stm32f429xx.h:163
I2S3ext
#define I2S3ext
Definition: stm32f4xx.h:1156
GPIO_ODR_ODR_8
#define GPIO_ODR_ODR_8
Definition: stm32f4xx.h:4506
UART4
#define UART4
Definition: stm32f4xx.h:1159
TIM5_IRQn
Definition: stm32f429xx.h:146
DMA2_Stream2_BASE
#define DMA2_Stream2_BASE
Definition: stm32f4xx.h:1106
GPIOK_BASE
#define GPIOK_BASE
Definition: stm32f429xx.h:1150
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f4xx.h:435
NonMaskableInt_IRQn
Definition: stm32f429xx.h:87
I2C1
#define I2C1
Definition: stm32f4xx.h:1161
I2C3_BASE
#define I2C3_BASE
Definition: stm32f4xx.h:1058
RTC
#define RTC
Definition: stm32f4xx.h:1150
FMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f429xx.h:560
GPIO_IDR_IDR_10
#define GPIO_IDR_IDR_10
Definition: stm32f4xx.h:4473
GPIO_ODR_ODR_11
#define GPIO_ODR_ODR_11
Definition: stm32f4xx.h:4509
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f4xx.h:360
SPI3_BASE
#define SPI3_BASE
Definition: stm32f4xx.h:1050
TIM14
#define TIM14
Definition: stm32f4xx.h:1149
CAN1_RX1_IRQn
Definition: stm32f429xx.h:117
UART8_BASE
#define UART8_BASE
Definition: stm32f429xx.h:1111
OTG_HS_WKUP_IRQn
Definition: stm32f429xx.h:172
FMC_R_BASE
#define FMC_R_BASE
Definition: stm32f429xx.h:1063
CAN2_RX0_IRQn
Definition: stm32f429xx.h:160
SYSCFG_PMC_MII_RMII_SEL
#define SYSCFG_PMC_MII_RMII_SEL
Definition: stm32f4xx.h:5837
ADC1
#define ADC1
Definition: stm32f4xx.h:1173
FMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f429xx.h:554
DMA1_Stream7
#define DMA1_Stream7
Definition: stm32f4xx.h:1203
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f4xx.h:744
USART1_IRQn
Definition: stm32f429xx.h:133
SAI1_Block_A
#define SAI1_Block_A
Definition: stm32f429xx.h:1265
DMA2_Stream0
#define DMA2_Stream0
Definition: stm32f4xx.h:1205
TIM2_IRQn
Definition: stm32f429xx.h:124
RTC_BASE
#define RTC_BASE
Definition: stm32f4xx.h:1045
EXTI_BASE
#define EXTI_BASE
Definition: stm32f4xx.h:1076
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f4xx.h:480
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f4xx.h:397
FMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f429xx.h:559
USART2
#define USART2
Definition: stm32f4xx.h:1157
SPI4_IRQn
Definition: stm32f429xx.h:179
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f429xx.h:999
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f4xx.h:758
SPI6_BASE
#define SPI6_BASE
Definition: stm32f429xx.h:1131
GPIO_IDR_IDR_9
#define GPIO_IDR_IDR_9
Definition: stm32f4xx.h:4472
TIM7
#define TIM7
Definition: stm32f4xx.h:1146
SVCall_IRQn
Definition: stm32f429xx.h:91
CAN_TypeDef::RESERVED5
uint32_t RESERVED5[8]
Definition: stm32f4xx.h:399
GPIO_TypeDef::AFR
__IO uint32_t AFR[2]
Definition: stm32f4xx.h:667
LTDC
#define LTDC
Definition: stm32f429xx.h:1267
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